Toshiba Cost Model for 3D NAND

Toshiba Cost Model for 3D NAND
by Fred Chen on 10-11-2020 at 8:00 am

Toshiba Cost Model for 3D NAND

Toshiba (now known as Kioxia) was the first company to propose a 3D stacked version of NAND Flash memory called BICS [1]. BICS (BICost Scalable) Flash used explicit process cost reduction based on depositing and etching multiple layers at once, avoiding multiple lithography steps. This strategy replaced the usual approach… Read More


Fully Self-Aligned 6-Track and 7-Track Cell Process Integration

Fully Self-Aligned 6-Track and 7-Track Cell Process Integration
by Fred Chen on 08-23-2020 at 6:00 am

Fully Self Aligned 6 Track and 7 Track Cell Process Integration

For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).

Figure 1. Left: a 7-track cell. Right: a 6-track cell.

This is a fundamental vulnerability for lithography, as defocus can change… Read More


Application-Specific Lithography: a 28 nm Pitch DRAM Active Area

Application-Specific Lithography: a 28 nm Pitch DRAM Active Area
by Fred Chen on 07-19-2020 at 2:00 pm

Application Specific Lithography 28 nm Pitch DRAM Active Area

In the recent DRAM jargon, “1X”, “1Y”, “1Z”, etc. have been used to express all the sub-20 nm process generations. It is almost possible now to match them to real numbers which are roughly the half-pitch of the DRAM active area, such as 1X=18, 1Y ~ 17, etc. At this rate, 14 nm is somewhere around

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Application-Specific Lithography: The 5nm 6-Track Cell

Application-Specific Lithography: The 5nm 6-Track Cell
by Fred Chen on 07-05-2020 at 10:00 am

Application Specific Lithography The 5nm 6 Track Cell

The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative case as its ‘7nm’ case [1]. TSMC had some published 5nm test structures which looked like… Read More


Feature-Selective Etching in SAQP for Sub-20 nm Patterning

Feature-Selective Etching in SAQP for Sub-20 nm Patterning
by Fred Chen on 06-02-2020 at 10:00 am

Feature Selective Etching in SAQP for Sub 20 nm Patterning

Self-aligned quadruple patterning (SAQP) is the most widely available technology used for patterning feature pitches less than 38 nm, with a projected capability to reach 19 nm pitch. It is actually an integration of multiple process steps, already being used to pattern the fins of FinFETs [1] and 1X DRAM [2]. These steps, shown… Read More


Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)

Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)
by Daniel Nenni on 01-28-2020 at 10:00 am

Our friends at Threshold Systems have a new class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last May. As part of the previous class we did a five part series on The Evolution of the Extension Implant which you can see on the Threshold Systems SemiWiki landing page HERE. And… Read More


The Evolution of the Extension Implant Part II

The Evolution of the Extension Implant Part II
by Daniel Nenni on 05-02-2019 at 7:00 am

The use of hard masks instead of photoresist for the Extension implant is an effective way to optimize the amount of dopant that is retained along the fin sidewalls for those fins that border along photoresist edges (as discussed in Part 1 of this series).

However, hard masks do nothing to address the dominant problem driving steeper… Read More


Changes Coming at the Top in Semiconductor Equipment Ranking

Changes Coming at the Top in Semiconductor Equipment Ranking
by Robert Castellano on 12-10-2018 at 12:00 pm

Semiconductor equipment vendor ranking, which didn’t change much between 2016 and 2017, is undergoing a makeover, as Lam Research, ASML, and Tokyo Electron (TEL) are switching places and top-ranked Applied Materials is getting closer to losing its number one ranking.

Since the 1990s, Applied Materials has been the market leader… Read More


Intel 10nm Yield Issues

Intel 10nm Yield Issues
by Scotten Jones on 04-29-2018 at 4:00 pm

On their first quarter earnings call Intel announced that volume production of 10nm has been moved from the second half of 2018 to 2019 due to yield issues. Specifically, they are shipping 10nm in low volume now, but yield improvement has been slower than anticipated. They report that they understand the yield issues but that improvements… Read More


SPIE 2017 – imec papers and interview

SPIE 2017 – imec papers and interview
by Scotten Jones on 04-28-2017 at 12:00 pm

At the SPIE Advanced Lithography Conference imec published a number of papers on EUV, multi-patterning and other lithography issues. In addition to seeing several of the papers presented I had a chance to sit down with imec’s director of advanced patterning, Greg McIntyre. In this article I will summarize my discussions… Read More