TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their… Read More


Design Technology CoOptimization at SPIE 2020

Design Technology CoOptimization at SPIE 2020
by Daniel Nenni on 02-14-2020 at 6:00 am

DTCO Fig1 SPIE2020 Semiwiki

SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More


SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More


Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!

Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!
by Scotten Jones on 03-29-2017 at 4:00 pm

Yesterday I attended Intel’s manufacturing day. This was the first manufacturing day Intel has held in three years and according to Intel their most in depth ever.

Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers – GLOBALFOUNDRIES, Intel, Samsung… Read More


An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes

An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes
by Scotten Jones on 02-28-2017 at 12:00 pm

At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.… Read More


ARM on Moore’s Law at 50: Are we planning for retirement?

ARM on Moore’s Law at 50: Are we planning for retirement?
by Scotten Jones on 01-16-2016 at 7:00 am

On Monday morning on December 7, 2016 Greg Yeric of Arm gave an excellent and wide ranging plenary talk at IEDM entitled “Moore’s Law at 50: Are we planning for retirement?”. You can download Greg’s slide deck here.… Read More


Imec’s An Steegen Talks Future Process Technology

Imec’s An Steegen Talks Future Process Technology
by Paul McLellan on 06-27-2015 at 7:00 am

I’m an An Steegen groupie. Once or twice a year I see a presentation by her and it is a great summary in a ridiculously short period of time of all the potential upcoming semiconductor technologies. Yesterday was my annual fix at the imec Technology Forum (ITF). Today I got to sit down with her at the conference center.

An is different… Read More