SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization

SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization
by Mike Gianfagna on 12-26-2023 at 6:00 am

SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co Optimization

Preventing the propagation of systematic defects in today’s semiconductor design-to-fabrication process requires many validation, analysis and optimization steps. Tools involved in this process can include design rule checking (DRC), optical proximity correction (OPC) verification, mask writing and wafer printing… Read More


Semiconductor Devices: 3 Tricks to Device Innovation

Semiconductor Devices: 3 Tricks to Device Innovation
by Milind Welling on 09-22-2023 at 8:00 am

Semiconductor Devices 3 Tricks to Device Innovation 1

The semiconductor industry’s incredible juggernaut has been powered by device innovations at its very core. Moreover, present-day enterprises encounter immense competitive pressures and innovations are a key differentiator to maintain their competitive edge1.

“It wasn’t that Microsoft was so brilliant or cleverRead More


IEDM 2022 – Imec 4 Track Cell

IEDM 2022 – Imec 4 Track Cell
by Scotten Jones on 01-18-2023 at 6:00 am

2022 IEDM Presentation Session23 2 VictorVega Page 03

At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.

Logic designs are built up by standard cells such as inverters,… Read More


Design Technology Co-Optimization for TSMC’s N3HPC Process

Design Technology Co-Optimization for TSMC’s N3HPC Process
by Tom Dillinger on 11-02-2021 at 8:00 am

N3HPC performance comparison

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

One of the topics that L.C. … Read More


Technology Optimization for Magnetoresistive RAM (STT-MRAM)

Technology Optimization for Magnetoresistive RAM (STT-MRAM)
by Tom Dillinger on 01-06-2021 at 6:00 am

profile simulations

Spin-transfer torque magnetoresistive RAM (STT-MRAM) has emerged from several foundries as a very attractive IP option.  An introduction to MRAM technology from GLOBALFOUNDRIES was provided in this earlier SemiWiki article. [1]

Briefly, STT-MRAM is a non-volatile storage option with the following attractive characteristics… Read More


Imec Technology Forum and ASML

Imec Technology Forum and ASML
by Scotten Jones on 07-30-2020 at 6:00 am

itf usa 2020 martin van den brink Page 15

On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.

Luc Van Den Hove
Luc Van Den Hove is the… Read More


TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their… Read More


Design Technology CoOptimization at SPIE 2020

Design Technology CoOptimization at SPIE 2020
by Daniel Nenni on 02-14-2020 at 6:00 am

DTCO Fig1 SPIE2020 Semiwiki

SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More


SPIE 2017 ASML and Cadence EUV impact on place and route

SPIE 2017 ASML and Cadence EUV impact on place and route
by Scotten Jones on 04-13-2017 at 7:00 am

As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More


Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!

Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!
by Scotten Jones on 03-29-2017 at 4:00 pm

Yesterday I attended Intel’s manufacturing day. This was the first manufacturing day Intel has held in three years and according to Intel their most in depth ever.

Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers – GLOBALFOUNDRIES, Intel, Samsung… Read More