SLiC Library tool dramatically accelerates DTCO for 3nm and beyond
In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by … Read More
As feature sizes have shrunk, the semiconductor industry has moved from simple, single-exposure lithography solutions to increasingly complex resolution-enhancement techniques and multi-patterning. Where the design on a mask once matched the image that would be produced on the wafer, today the mask and resulting image … Read More
Yesterday I attended Intel’s manufacturing day. This was the first manufacturing day Intel has held in three years and according to Intel their most in depth ever.
Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers – GLOBALFOUNDRIES, Intel, Samsung… Read More
At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.… Read More
On Monday morning on December 7, 2016 Greg Yeric of Arm gave an excellent and wide ranging plenary talk at IEDM entitled “Moore’s Law at 50: Are we planning for retirement?”. You can download Greg’s slide deck here.… Read More
I’m an An Steegen groupie. Once or twice a year I see a presentation by her and it is a great summary in a ridiculously short period of time of all the potential upcoming semiconductor technologies. Yesterday was my annual fix at the imec Technology Forum (ITF). Today I got to sit down with her at the conference center.
An is different… Read More