The time is nigh for another meeting of the practitioners of the lithographic arts, dark and otherwise, at the SPIE Advanced Lithography symposium.
I love this conference for the engagement you see, both in the sessions and in the hallways. People actually meet and talk and argue. There’s always interesting gossip, exciting technologies, and spirited debate about the future of lithography. Each year, you also see more DFM topics. SPIE is like the bridge of a great ship from which you can witness the merging of two, once-separate, seas. Just take a peek at the program and you’ll notice the significant presence of DFM, or more broadly (as one of the conferences is eloquently titled), “design-process-technology co-optimization for manufacturability.”
In fact, one-third of the plenary presentations on Monday, February 24, covers the topic of the design-manufacturing-test flow, specifically, dealing with patterns throughout the design and manufacturing flow. The presenter is Joseph Sawicki, VP of the Design-Silicon division at Mentor Graphics, and the premise is that design style-based or systematic defects have become major challenges to yield ramp. The defects are driven by the difficulty in lithography at advanced nodes. Part of the solution is to be found in EDA software. He will discuss some of these EDA-based yield solutions that span design, manufacturing, and test. He refers to this set of EDA tools as a “pattern-aware” EDA flow and says it will minimize risk and enhance manufacturing.
For example, there are powerful new methods of identifying pattern failures hiding in yield loss. While diagnosis-driven yield analysis has been around for a while, the new generations of this software-based diagnosis of test failures includes integration with DFM tools and new algorithms that remove the noise, or ambiguity, from the statistical analysis. In practice, this means finding the offending defect quickly and with high confidence.
Another EDA technology Sawicki will mention is new OPC methods. Mentor engineers have a number of papers at SPIE about model-based OPC, SEM-countour based OPC model calibration, resist toploss modeling, and neighbor-aware fragment feedback with “matrix” OPC, among others. Sawicki will also talk about technologies that will be ready to help find and fix failure mechanisms in emerging process nodes and tools that give designers visibility into the risks of production.
Sawicki is a dynamic speaker, and the topic is timely. Process ramp and yield ramp is under pressure at the emerging nodes, and I can verify that this trend has kicked EDA innovation into high gear. SPIE is February 23-27 at the San Jose convention center. Pre-registration ends Feb 19, so sign up now online. You can still register in person the day of the event.