There was an article on Motley Fool recently detailing Intel’s 14nm FinFETs and comparing them to TSMC. Unfortunately the author has zero semiconductor education or experience even though he writes with authority on all things semiconductor. He also has no shame in using outdated papers from conferences he did not even attend to make his misguided point. The things people do for a penny per click… and yes I did speak to him privately about this but he stands by his article and left it to me to prove him wrong, which is why I write this now.
Intel Corporation to Detail 14-Nanometer System-on-Chip Technology at VLSI Symposium
According to SemiWiki experts, Motley Fool’s article misrepresents some of the intricacies associated with FinFets and how drive currents are defined. On the face of it, Intel’s 14nm announcement looks impressive; 37-50% drive current improvements over 22nm, who could complain about that? Unfortunately a slightly deeper dive reveals some issues with this conclusion. Intel, at various meetings, including their analyst meeting back in November 2014, proudly announced their fin pitch scaled from 60nm to 42nm, while their fin height increased from 34nm to 42nm. All good assuming I have similar current/micron of fin perimeter (also called Weff which for one fin is 2* height + top width, but more on that later). With more fins/micron and taller fins, I should be able to have much better performance.
However, if you read their IEDM 2014 paper carefully, you will notice that all Intel’s drive current numbers are quoted per micron of drawn width, i.e. for one micron of top view silicon width. Now taking the assumption above of same current/micron of fin perimeter, how much performance improvement should I get per drawn micron? Using Intel’s own numbers, we have 60/42 =1.43X more fins/micron and fins are 42/34 = 1.24X taller, so all in all we should get 1.76X more drive current/drawn micron. In others words, at equal drive current per micron of fin perimeter, we should have seen 76% more current from these tighter taller fins, but Intel is reporting only 37-50%. Clearly the drive current per effective micron is going down. Intel struggled with their 14nm yield, this suggests they may have also struggled with their device performance.
The article goes on to compare Intel to TSMC 16nm FinFet however the author does not realize that the TSMC 2013 IEDM paper was quoting drive currents/Weff as described above, not per drawn micron. TSMC actually pointed this out in their 2014 IEDM presentation. TSMC also showed even better performance in their 2014 paper than the earlier 2013 version, hence the new process name 16FF+. So in the end, how do they stack up? If you use the Intel’s per drawn micron metric, TSMC 16FF+ has ~10% more drive current than Intel 14nm (all other things being equal including leakage and voltage). If you use another metric like current/fin, or current/Weff, TSMC has an even stronger advantage.
That is why during the TSMC symposium last month Dr. BJ Woo emphatically stated TSMC had “the best” transistor in the 14-16nm technologies. It will be interesting to watch how this unfolds as 10nm process details are disclosed. In my 30 years in the semiconductor industry I don’t remember a more exciting time, absolutely.