Tag: pdk

Webinar: Foundry-Compatible Customized Designs with AIM Photonics PDK and KLayout

Webinar: Foundry-Compatible Customized Designs with AIM Photonics PDK and KLayout
by Admin on 02-06-2023 at 1:42 pm

Join our experts as they demonstrate layout-driven workflows in KLayout via an example design, simulation, and compact model generation of a custom multi-mode interference (MMI) splitter compatible with the AIM Photonics PDK process. This webinar will also demonstrate creating a photonic circuit using customized and foundry-validated

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AMS IC Designers need Full Tool Flows

AMS IC Designers need Full Tool Flows
by Daniel Payne on 08-31-2021 at 10:00 am
Categories: EDA, Siemens EDA

AMS tool flow min

Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera,  accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal  IC design comes… Read More

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Another Smart EDA Merger Adds RF Tools

Another Smart EDA Merger Adds RF Tools
by Daniel Payne on 12-12-2019 at 10:00 am
Categories: Cadence, EDA
5 Comments

Cadence acquires AWR

Mergers and acquisitions are just a fact of modern business life, so the semiconductor, IP and EDA industries all can benefit, but only when the two companies have complementary products with some actual synergy. Cadence acquired OrCAD back in 1999, adding a Windows-based PCB tool to their product lineup, and here in 2019 some … Read More

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TSMC Design Platforms Driving Next-Gen Applications

TSMC Design Platforms Driving Next-Gen Applications
by Daniel Nenni on 03-03-2017 at 7:00 am
Categories: AI, Automotive, FinFET, Foundries, IoT, Mobile, TSMC

Coming up is the 23rd annual TSMC Technology Symposium where you can get first-hand updates on advanced and specialty technologies, advanced backend capabilities, future development plans, and network with hundreds of TSMC’s customers and partners. This year the Silicon Valley event kicks off at the Santa Clara Convention… Read More

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Is That PDK Safe to Use Yet?

Is That PDK Safe to Use Yet?
by Daniel Payne on 10-28-2016 at 12:00 pm
Categories: EDA, Platform Design Automation

In our semiconductor ecosystem we have foundries on one side supplying all of that amazing silicon technology, and IC designers on the other side that take their system ideas then go implement them in a SoC using a specific foundry. The required interface between foundry and chip designers has been the Process Design Kit (PDK), … Read More

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TSMC and Solido to Share Experiences with Managing Variation in Webinar

TSMC and Solido to Share Experiences with Managing Variation in Webinar
by Tom Simon on 09-10-2016 at 7:00 am
Categories: EDA, Foundries, Solido, Synopsys, TSMC

TSMC knows better than anyone the effect that variation can have at advanced process nodes. Particularly in memory designs and in standard cell designs, variation has become a very critical because of its effects on yield and because of the high-cost of compensating for it. Smaller feature sizes combined with lower voltage thresholds… Read More

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A Brief History of Platform Design Automation

A Brief History of Platform Design Automation
by Daniel Payne on 07-01-2016 at 12:00 pm
Categories: EDA, Platform Design Automation

Two weeks ago I spoke on the phone with Albert Li, Founder and CEO of Platform DA about his EDA company. Prior to founding Platform DA in Beijing, Li worked at Accelicon which was acquired by Agilent in December 2011. Mr. Li graduated from Tsinghua University and Vanderbilt University, both in Electrical Engineering, and has written… Read More

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Does Managing Tools as if they are IP Make Sense?

Does Managing Tools as if they are IP Make Sense?
by Tom Simon on 12-10-2015 at 7:00 am
Categories: EDA, Methodics

Years ago I thought that chip design companies would embrace the latest technology and be eager to adopt new tools. What I learned was that the people implementing and managing design projects were taking a lot of risks with almost every aspect of their projects. What they most wanted is to minimize risk from the design process – especially… Read More

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A FinFET BSIM-CMG model update from UC-Berkeley

A FinFET BSIM-CMG model update from UC-Berkeley
by Tom Dillinger on 10-06-2015 at 4:00 pm
Categories: EDA

Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php… Read More

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Boost the Market for Interposer and 3D ICs with Assembly Design Kits

Boost the Market for Interposer and 3D ICs with Assembly Design Kits
by Beth Martin on 07-29-2015 at 6:00 pm
Categories: EDA, Siemens EDA

The traditional system-on-chip (SoC) design process has fully qualified verification methods embodied in the form of process design kits (PDKs). Why is it that chip design companies and assembly houses have no IC/package co-design sign-off verification process?

Package die are often produced using multiple processes and… Read More