Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php .
This model qualification is a key milestone, as it enables EDA vendors to adapt their circuit simulation tools accordingly, with the knowledge that foundries will provide corresponding technology process parameters for this model in their process design kit (PDK) releases. (Foundries may add a software layer on top of these underlying models, to provide additional functionality – e.g, TSMC’s Technology Model Interface, or TMI.)
The initial FinFET process technology model endorsed by the CMC was the BSIM-CMG format in March, 2012, from the theoretical device modeling team at the University of California-Berkeley (CMG = Common Multi-Gate FinFET topology):http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG
This site includes the current model documentation and source code.
The existing model made some simplifying assumptions when solving field/charge distribution equations, most notably that the fin cross-sections were rectangular. The initial fins from the fabs were most definitely not rectangular:
The BSIM modeling team at UC-B has developed an enhanced FinFET model format, to support an arbitrary fin profile, as described in their recent VLSI Technology Symposium technical paper:
Khandelwal., S., et al, “New Industry Standard FinFET Compact Model for Future Technology Nodes”, 2015 Symposium on VLSI Technology, paper 6-4, pages T62-63.
Rather than rectangular measures of fin height and thickness as inputs, the new field/charge model formulation uses the fin area, perimeter, and gate-to-channel capacitance to describe the (arbitrary) fin profile.
This new model also incorporates additional features, in anticipation of new fin materials and/or different device construction (e.g., for the 5nm process node):
- a pFET fin channel comprised of Germanium (requiring unique mobility modeling support)
- an nFET fin channel comprised of a III-V semiconductor (with unique mobility modeling for InGaAs)
- a new model formulation for the “density-of-states” energy levels and free carrier occupation
- new model support for a gate-all-around (GAA, or “nanowire”) device topology
Note that the electric field-dependent carrier mobility equations are significantly different for Germanium and (especially) III-V materials from Silicon.
Also, at very small dimensions, the density of free (electron/hole) states in the channel at the (conduction/valence) band edges is limited – a unique carrier density versus energy calculation is required. The net result is the device currents are reduced.
The expectations for this new model are better fitting accuracy to silicon, and better preparation for future process nodes, whether extending traditional fin technology with new materials, or the introduction of nanowires. The technical paper highlights examples of the improved fitting, both for 14nm FinFET’s and (early) GAA devices:
Of course, model accuracy is important, but not at the expense of the circuit simulation runtime, as a significant percentage of the calculations are within device models. The UC-B team profiled model performance and has also significantly enhanced the throughput with this new model.
The figure shows runtime comparisons between the current and proposed models for field/charge calculations, the temperature- and voltage-dependent equations, and the total execution time. (Runtime results for both bulk FinFET’s and FinFET’s fabricated on an SOI layer are shown.)
The CMC qualification and EDA vendor simulation plus foundry PDK techfile support for this new, increased accuracy model is still in flight. Ideally, the impact of this transition to designers will be as straightforward as installing a new release. (It wouldn’t hurt to contact your CMC council representative to encourage a prompt review of this new model, as the performance improvements alone are compelling.)
To be sure, there are still plenty of model development challenges ahead.
The (mature) BSIM models for planar FET devices include current-modifying parameters representing layout-dependent and materials stress effects. The related layout widths and spacings around the modeled devices as included as base BSIM model parameters:
FinFET’s add the complication of “N fins per layout finger”, where layout-dependent effects (LDE’s) may modulate the behavior of edge fins relative to internal fins.
That level of maturity is not yet reflected in the BSIM-CMG model. For example, LDE’s must currently be supported as part of the foundry’s software algorithms, which then invoke the underlying BSIM-CMG code.
Kudos to the BSIM-CMG model development team for their recent breakthrough!
Look for ongoing enhancements from the team to this new “arbitrary fin profile” model. And, look for announcements from the CMC, both for their endorsement of this latest model format, and approval of a (relatively new) initiative for a standard application programming interface for the foundry’s software layer that invokes the BSIM-CMG model.
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