Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when using a STA tool. Brandon Bautz, Senior Product Management Group Director, Digital & Signoff Group at Cadence walked me through some of these new analysis challenges, and their new Tempus DRA (Design Robustness Analysis) Suite:
Each of these five issues cause variation in the chip timing results, which can lead to intermittent failures in ICs, so a timing signoff tool must bound the distribution of variation. The first challenge listed is aging robustness, and this deals with the transistor Vt and IV curve changing over time, based on how often each transistor is toggled, how great the voltage swing is, and at what temperature the transistor is operating at. With older process nodes you could make the simplifying assumption that all transistors aged at the same rate, however with new process nodes the transistor aging is non-uniform across the chip, so that has to be taken into account now.
The Tempus tool for STA gets the aging information it needs from the Liberate tool used during standard cell characterization runs. So, Tempus knows how to handle the non-uniform aging challenge, providing the most accurate timing numbers based on stimulus from logic simulation plus a calendar age.
As currents flow through VDD and VSS interconnect the parasitic resistances create a voltage drop, and that in turn impacts timing through the cells. The Tempus PI (Power Integrity) tool uses the IR drop values to produce a more accurate STA number. Using Voltus (EM/IR drop) and Tempus together helps designers locate timing critical layout areas and reduce the impact of voltage variation.
Process variations impact timing values, so the idea is to analyze the full chip to find areas of high process variation and then how it effects timing of cells along a critical path. Knowing how timing variation is caused by process variation is another method like signoff slack to indicate how robust timing is.
Foundries release Process Design Kits (PDK) and update the versions as they tune the silicon for that node over its useful lifetime. IC designers want to know how much the performance of their chip will change as PDK matures from version 0.5 to 0.7 to 1.0. The Liberate tool captures variation between the old and new PDKs without requiring a full library re-characterization. The designer may then use Tempus to analyze the timing impact of the new PDK on the design.
VT Skew Robustness
Current STA approaches can be pessimistic in applying VT Skew, so a new approach using skew to perform analysis at one corner for each Vt class in order to move delays towards others. For example, when analyzing the TT corner with slow and fast derate to move delays towards SSG and FFG corners.
As process nodes became smaller, then more accuracy in modeling was required, so Cadence has updated their Tempus tool for STA to account for aging robustness, voltage robustness, timing robustness, silicon prediction and VT skew robustness. This improved modeling and analysis meanings more accurate timing compared to silicon, resulting in fewer silicon spins.
Read more about the Tempus DRA Suite.
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