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Uniquely Understanding Challenges of Chip Design and Verification

Uniquely Understanding Challenges of Chip Design and Verification
by Daniel Nenni on 11-14-2023 at 6:00 am

Jean Marie Brunet chip designJean-Marie Brunet is Vice President and General Manager of Siemens Hardware-Assisted Verification. He and I spoke recently about how different his hardware group is from the rest of the software-centric EDA product space and why a hardware-oriented EDA vendor like Siemens fully understands the challenges of the chip design and verification community.

Siemens EDA is a hardware-assisted verification provider with a unique vantage point for an EDA vendor. Explain why.
Yes, we have a unique vantage point because we happen to practice the same thing as our customers. We design and verify our own chips just like they do and obviously practice what we are offering. We are exposed to the same problems that our customers are exposed to in terms of challenges and how big chips get verified.

Every new generation of our chip gets verified by the current emulator generation, giving us insight and understanding into our challenges and those of our customers. I believe it gives us far more credibility when we speak to customers, as well as credibility in understanding industry trends. Since we design complex devices, we understand the verification trends because we’re going through them ourselves. It’s an important consideration for companies evaluating their hardware-assisted verification (HAV) providers.

Some other HAV vendors have the same perspective we do because they design their chips, but not all because they don’t design and verify their own chips.

Hardware-assisted verification is a different market segment than typical EDA and a difficult one for startups.
The difference between doing a startup in the hardware domain versus an EDA software startup is fundamental. The cost structure on the software side is mainly headcount and that can scale. The startup that does hardware means a CapEx investment to create the hardware and it needs to raise far more money to get started. The entry point of investment is much higher than software.

It’s a difficult market for startups that must have the ability to serve efficiently and completely and where investment and scaling are needed. I know how much it costs to design hardware. It’s difficult and a high expense.  The investment is not peanuts in terms of advancement. Clearly, it’s a market for large companies because it requires a complete offering and customers’ challenges require a complete set of offerings –– not one small piece.

How do you define the hardware-assisted verification market?
In general, anyone looking at the combined hardware-assisted verification market that is FPGA based and custom ASIC based doesn’t make the distinction and assumes it’s a lump sum market.

One segment of the market is driven by FPGA devices. The recent AMD launch where we actively participated defines an envelope of what can be done with a hardware architecture that integrates FPGAs. The FPGA space is well defined and serves a market in need of performance and the ability to run faster but less able to debug than the platform in the other market.

The other market is more about debuggability and how the hardware will scale. If an engineering group is at the stage or what we call emulation, it has a well-defined envelope and market space serving the SoC debug stage. It is far more efficient at SoC bug and tailored for fast compilation, debug and scaling.

By separating the tools and the markets, it’s easy to identify the use models and match the type of hardware and architecture. The overall market is growing tremendously because of trends that are not slowing down at all. They are accelerating.

All the market analysts are predicting continued growth. We see demand for HAV continuing for at least the next five years. This is an important segment and there are things that have happened in this space. With two domains –– hardware based on an FPGA chip from a third party or hardware based on a chip designed in house and based on an FPGA device.

What trends are you seeing?
The HAV market has dynamic changes going on and it’s important to understand the dynamic trends to predict the next five years and keep up with what’s happening with Moore’s Law and More than Moore. It’s also important to keep up with market demand and the cost increases of producing devices. One of the key trends that we see is ML and AI content in many devices. This drives a need for software shift left and scalable capacity.

Jean-Marie Brunet
Jean-Marie Brunet is the Vice President and General Manager of the Hardware-Assisted Verification at Siemens EDA. He has served for over 25 years in management roles in marketing, application engineering, product management and product engineering roles in the EDA industry and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron among others. Jean-Marie holds a master’s degree in electrical engineering from I.S.E.N Electronic Engineering School in Lille, France.

Also Read:

Make Your RISC-V Product a Fruitful Endeavor

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

The Path to Chiplet Architecture

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