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RISC-V
Posted on by Daniel Nenni

Make Your RISC-V Product a Fruitful Endeavor

Make Your RISC-V Product a Fruitful Endeavor
by Daniel Nenni on 11-06-2023 at 6:00 am
Categories: EDA, RISC-V, Siemens EDA
1 Comment

RISC-V Chip

Consider RISC-V ISA as a new ‘unforbidden fruit’. Unlike other fruits (ISAs) that grow in proprietary orchards, RISC-V is available to all, i.e. open-source. Much like a delicious fruit can be transformed into a wide array of delectable desserts, so can RISC-V be utilized to create a plethora of effective applications across industries—consumer, industrial, medical, and mil-aero, to name a few.

The farm-to-table journey bears a great resemblance to the design-to-application journey. Considering that the hardware acts as the pots and pans that define and determine the scope of the end-application. There is no dearth of industry titans manufacturing these implements. Storage giant Western Digital is not only moving production hardware to RISC-V, they have also released their own RISC-V-based SweRV Core™ to the open-source community; graphics leader NVIDIA has decided to base their next-generation Falcon logic controller on RISC-V. Semico Research estimates that by 2025 there will be over 62 billion RISC-V-based devices shipped globally.

In this analogy, if your hardware is the pots and pans used to make said dessert, your software plays the role of the recipe and the cooking medium. A recipe describes the full set of processes to be applied to your ingredient(s). Somewhat similarly, the compiler, libraries, linker and debugger tool set used to convert application source code to binary code and get it running on the target hardware, are collectively referred to as a toolchain. Toolchains integrated into an application development suite to support a specific product are known as a Software Development Kit (SDK) which is a key part of the ecosystem needed to support RISV-C commercial product deployment.

Now, you can download any old recipe from the internet and with some skill, come out with something delicious. Software developers targeting RISC-V devices are certainly free to download GCC or LLVM source code directly from the projects’ public open-source repositories. However, this is not usually an efficient first step in porting application software to a RISC-V processor. Building and validating your own open-source-based toolchain is a complex and lengthy process fraught with many potential pitfalls, especially for those new to building their own toolchains.

Fortunately, many RISC-V chip and IP vendors provide open-source-based toolchain reference distributions to help developers to evaluate their IP. While these reference toolchains are useful for evaluating RISC-V IP, there are no productized solutions to enable developers and end users to deploy software applications to commercial RISC-V-based products. There are three key requirements to consider when procuring customer ready open-source-based toolchains to enable developers to use RISC-V based platform–commercialization, customization, and support.

Commercialization

Toolchain commercialization is the process of transforming the publicly available open-source code into a tested and supportable distribution of executable toolchain components and libraries configured to support the target devices. The two most important toolchain commercialization considerations are selection of the compiler version as well as the target device variants to be supported. The commercialization process leverages the open-source compiler project test suites and test frameworks, such as DejaGNU, to provide toolchain test coverage. Such coverages ensures high-quality toolchains built from a rapidly changing code base.

Customization

Toolchain customization provides feature extensions and performance optimizations beyond what is currently available from the open-source community. For RISC-V, toolchain customization can take the form of compiler extensions to support hardware vendor-specific RISC-V ISA or customizations enabled via the RISC-V open ISA. Target-specific application performance optimization is another area of toolchain customization that can help maximize target hardware application performance. In addition, toolchain customization can also include compiler bug fixes and new feature completion not yet publicly available from the open-source community.

Support

Toolchains regularly have CVEs reported against them, including issues in the compiler runtime libraries. Undiscovered CVEs in compiler runtime libraries get linked into application software and can thus be inadvertently deployed to customers via a product release. This, in turn, creates the risk of having to provide a hot-fix software update to address newly discovered CVEs at some point in the future. In such cases having a toolchain support contract in place that provides ongoing CVE remediation will ensure your toolchain is ready to build the software update needed to resolve such a crisis quickly and effectively without having to first sort out potentially years of toolchain patches and updates. Toolchain long-term support is intended to keep older version toolchains updated with critical CVE patches and bug fixes while minimizing the total number of overall toolchain changes to reduce the risk of introducing new issues.

As RISC-V enters the mainstream of embedded commercial products, a customer-ready software development ecosystem will be essential for marketplace success. Toolchain commercialization, customization and support are essential ingredients for deploying commercial grade open-source based toolchains in SDKs supporting RISC-V based product development and post release software updates. Siemens has a 20+ year proven track record in delivering commercial-grade toolchains and toolchain support services for a wide variety of processor architectures.

Managing a RISC-V operation yourself is hard. A commercialized product can be the difference between a home-cook and a professional chef. The latter has significantly more expertise and can make life far easier. A customized, commercialized product with ongoing support can deliver a smooth execution that will make you want to celebrate with dessert.

Article provided by the Embedded Software Division, Siemens Digital Industries Software.

Also Read:

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

The Path to Chiplet Architecture

Placement and Clocks for HPC

 

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