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SoC Verification Closure Pushes New Paradigms

SoC Verification Closure Pushes New Paradigms
by Pawan Fangaria on 02-06-2014 at 10:00 am

In the current decade of SoCs, semiconductor design size and complexity has grown by unprecedented scale in terms of gate density, number of IPs, memory blocks, analog and digital content and so on; and yet expected to increase further by many folds. Given that level of design, it’s imperative that SoC verification challenge has gone much beyond that (more than 2/3[SUP]rd[/SUP] of design time is spent in verification) at an exponential rate; however verification resources have seen more or less incremental and scattered additions. Other than logic and timing simulation, multiple other verification methods have evolved such as formal, hardware assisted, embedded software, virtual and so on. Considering that the whole SoC has to be verified together in a reasonable time with accuracy, we must look at it from a different perspective of complete and fast design closure rather than only performance of certain steps in the verification flow, such as simulation speed. Of course, performance is very important, but that needs to be put to productive use with intelligent assignments (or tweaking) to reach the final verification closure, faster.

Last week, when I reviewed Cadence’snew release of Incisive 13.2 platform, I felt it is a real major leap in the right direction towards what an SoC verification needs today. Adam Sherer, Product Marketing Director at Cadence has described top 10 ways (by using Incisive 13.2 platform) to automate verification for highest levels of performance and productivity in his whitepaper posted at Cadence website. Although most of these methods provide multi-fold productivity improvement in verification, I was really impressed with some of those which focus at higher level of abstraction to complete the job by order of magnitude faster, yet with the same level of accuracy as gate level. Notable among them are –

a) X-Propagation FlowIncisive Enterprise Verifier formal app creates assertions (to resolve issues due to X-optimism of RTL such as Verilog which can often assign a ‘0’ or ‘1’ to evaluate a state which should actually be an ‘X’ as per gate logic; refer herefor details) that can be applied to X-propagation RTL simulation to monitor the generated X values. These X values created by logic, X-propagation or low-power simulation can then be identified in the SimVision debugger.

b) UVM Debug Enhancements– With SystemVerilog support (in addition to ‘e’) in Incisive Debug Analyzer, its integration with Incisive Enterprise Manager, and several enhancements in the SimVision unified graphical debugging environment, bugs can be found in minutes instead of hours and also debugging can be done in regression mode.

c) Digital Mixed SignalSystemVerilog (IEEE 1800-2012) real number modeling support in ‘Digital Mixed Signal Option’ of Incisive Enterprise Simulator enables user to model wave superposition at digital simulation speed, thus introducing a powerful capability in Incisive Enterprise Simulator to perform complete mixed-signal simulation without needing co-simulation with an analog solver.

d) Register Map Validation– Considering a design having 10s to 100s of thousands of control registers, it’s impossible to manually write tests and verify them. Incisive platform has Register Map Validation app that completes the job in a few hours as compared to weeks of simulation effort.

Further, finding a nice articleon this topic written by Richard Goeringwhich provided me a link to a webinaron Register Map Validation, I was delighted to go through the webinar to know about how exhaustive, efficient and easy that Register Map Validation is. Thanks to Jose Barandiaran, Senior Member of Consulting Staff and Pete Hardee, Director of Product Management at Cadence for presenting this nice webinar.

Using the simulation approach for register map validation can be very inefficient in terms of coverage and test time whereas the Register Map Validation App can automatically test the register with all meaningful activities; above is an example of RW access policy test.

Users can provide specific information such as protocol which is merged with register description in IP-XACT format by a ‘Merge Utility’ and the extended IP-XACT description is passed to the Register Validation Map App which automatically generates Bus Functional Model (BFM) and other checks that get verified through Incisive Enterprise Verifier.

Both, front door (writing to register) checking between the IP and BFM and back door (read) checking are done. Usually at the sub-system level, multiple IPs are interfaced through a bridge. Verilog, VHDL or mixed language can be used. All types of checking such as Read-only, RW, write one set, write one clear, read to set, read to clear, register value after reset and write-only (in case of back door) are done. The app also provides control over activity regions to check any corruption. Particular registers or fields can be specifically selected for test.

An easy to use SimVision GUI is provided for customized debugging to identify the particular bits in error, in particular phase of testing (front door or back door), register address, reset sequence and value etc. There is an interesting demo also during the webinar which shows live debugging and validation of registers. It’s an interesting webinar to go through!

Register Map Validation App enables designers to do exhaustive testing of register access policies. It significantly reduces verification time and enhances designers’ productivity with easy debugging. The Incisive Enterprise Verifier uses mixed approach of simulation and formal. Formal analysis is done statically in breadth first manner covering complete space. Assertion driven simulation is dynamic and linear requiring no testbench. Cadence is seeing rising customer base using Incisive Verification Apps.

More Articles by Pawan Fangaria…..

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