SoC Verification Closure Pushes New Paradigms

SoC Verification Closure Pushes New Paradigms
by Pawan Fangaria on 02-06-2014 at 10:00 am

In the current decade of SoCs, semiconductor design size and complexity has grown by unprecedented scale in terms of gate density, number of IPs, memory blocks, analog and digital content and so on; and yet expected to increase further by many folds. Given that level of design, it’s imperative that SoC verification challenge has… Read More


Because X doesn’t always mark the exact spot

Because X doesn’t always mark the exact spot
by Don Dingee on 11-30-2013 at 1:00 pm

Digital hardware has a habit of deciding – based on the bias and behavior of transistors – to drive outputs to a 0, or a 1, or if commanded a high-impedance Z state. SystemVerilog recognizes a fourth state: X, the “unknown” state a simulator has trouble inferring.

Simulators have a choice. Under X-optimism, they can convert the unknown… Read More