Cadence continues on its quest to be a top semiconductor IP supplier which is a good thing since the semiconductor world now revolves around IP. Cadence CEO Lip-Bu Tan mentioned IP 14 times during his keynote and he was followed by the president of Imagination Technologies and the CEO of recently acquired Tensilica. I was not afforded the slides for these presentations so we will leave it at that for now. I did sneak a quick photo of this slide which is a nice overview of the current Cadence IP offering.
Semiconductor IP will also be a focus at the IEEE EDPS conference next month. Last year I organized FinFET day, this year it will be IP day:
If you look at the Semiconductor IP usage trends over the last five process nodes (65nm, 40nm, 28nm, 20nm, 16nm) the number of unique IP per tape-out is increasing while the ability to re-use IP across nodes is dropping. And thanks to the ultracompetitive mobile market with new products coming at us every day, design cycles are incredibly short and complex. In this session we will explore the Semiconductor IP challenges facing the fabless semiconductor ecosystem.
Coincidentally, Cadence VP of IP Martin Lund will be keynoting:
Every chip is different. So the promise of IP that will work for all doesn’t quite match up to reality. Even with standards-based IP, design teams often request specialized interfaces, memory structures, and other changes so the IP fits better in their SoC. How close are the IP companies getting to delivering IP the way chip designers really want? How close are we to the promised Lego-like approach to chip design with off-the shelf IP? And what are IP companies working on to close the gap?
Also joining us at the podium:
eSilicon: Patrick Soheili, VP, Business Development and VP and GM, IP Solutions
IPextreme:Warren Savage President and CEO
Arteris:Kurt Shuler VP Marketing
TSMC:Lluis Paris,Deputy Director, IP Portfolio Management
Mentor:Carey Robertson, Director of Product Marketing, Mentor Graphics
Atrenta:Bernard Murphy CTO
And my most favorite EDA CEO, Wally Rhines, will be keynoting the Thursday night dinner:
THE BIG SQUEEZE
For decades, we’ve known it was coming and now it’s here. Moore’s Law-which is really just a special case of the “learning curve”-can no longer drive the 30% per year reduction in cost per transistor, beginning with the 20/16/14 nm generation. Either we find innovations beyond just shrinking feature sizes and increasing wafer diameter or we slow our progress down the learning curve, introducing innovative new electronic capabilities at a slower rate than in the past. There are lots of alternatives, including a reduction in profitability of the members of the supply chain, to keep the progress continuing at the same rate as the last fifty years. Dr. Rhines will review the mathematical basis for the dilemma and, with his brand of humor, provide a roadmap of possibilities for the decade ahead.
EDPS Early bird registration is open now, I hope to see you there!