Cadence today announced that it is acquiring Forte Design Systems. Forte was the earliest of the high-level synthesis (HLS) companies. There were earlier products. Synopsys had Behavioral Compiler and Cadence had a product whose name I forget (Visual Architect?), but both products were too early and were canceled. Cadence internally developed their own high-level synthesis product called C-to-Silicon compiler. The market is now ready for adopting high-level synthesis. Xilinx purchased autoESL a couple of years ago and are aggressively pushing designers to a higher level, mainly so that software engineers who have never even heard of Verilog can use Xilinx products to create hardware accelerators for parts of their software when pure code is either too slow or too power hungry. Calypto is selling Catapult, which used to be Mentor’s offering in the space. Synopsys purchased Synfora although they don’t seem to be pushing into the space aggressively.
As Cadence said:Driven by increasing IP complexity and the need for rapid retargeting of IP to derivative architectures, the high-level synthesis market segment has grown beyond early adopters toward mainstream adoption, as design teams migrate from hand-coded RTL design to SystemC-based design and verification. The addition of Forte’s synthesis and IP products to the Cadence C-to-Silicon Compiler offering will enable Cadence to further drive a SystemC standard flow for design and multi-language verification.
It is actually a bit of an illusion that all HLS products are pretty much the same. HLS in general has been good for DSP algorithms where there is a fair bit of flexibility about trading off performance, power, throughput, latency and so on. But some approaches have focused on automatically taking very high level algorithms (such as recognizing moving objects in video) and others have focused on cleanly interfacing to complicated memory restrictions. Others are focused mainly on improving productivity, requiring fewer lines of code to get to the eventual implementaiton. The reality is that there often is less flexibility in the implementation than meets the eye but for sure HLS is at a higher level: fewer lines of code and written in C or C++, familiar to software engineers (and often also SystemC which typically is more of a hardware guy’s world).
Cadence again on how they see Forte as complementary to their existing C-to-Silicon offering:Forte brings high quality of results (QoR) for datapath-centric designs, world-class arithmetic IP, valuable SystemC IP and IP development tools. Forte’s Cynthesizer HLS product features strong support for memory scheduling, especially for highly parallel or pipelined designs. These strengths complement the high QoR for transaction-level modeling, under-the-hood RTL synthesis and incremental ECO support featured by Cadence C-to-Silicon Compiler.
I don’t know enough about the nitty-gritty under-the-hood details of either product although it is clear that the emphasis on their development has been different. Just how complementary they are remains to be see (would a customer buy both of them?) and I assume in time that the two technologies will be integrated together into a single HLS product—they don’t seem different enough to keep them as two separate product indefinitely. A lot of the IP that Forte has presumably will play in C-to-Silicon almost immediately.
The terms were not disclosed but Cadence say they expect it to be slightly accretive this year and accretive going forward, which I guess means the price was not extremely high. Accretive means that after the merger accounting, they will make more profit per $ of Forte product revenue than Cadence makes currently across its entire product line. Actually accretive means increasing EPS but it is almost the same thing.
Cadence press release is here.
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