Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow

Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow
by Admin on 10-04-2023 at 5:11 am

Date and time: Friday, November 10, 2023 15:00-16:00

Sponsor: Japan Cadence Design Systems, Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: November 9th (Thursday)

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Stratus HLS (High Level Synthesis) Seminar Series: [Part 4] Result analysis and microarchitecture exploration

Stratus HLS (High Level Synthesis) Seminar Series: [Part 4] Result analysis and microarchitecture exploration
by Admin on 10-04-2023 at 4:50 am

Date and time: October 13, 2023 (Friday) 15:00-16:00

Sponsor: Japan Cadence Design Systems, Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: October 12th (Thursday)

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Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging

Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging
by Admin on 08-31-2023 at 2:05 pm

Date: September 15, 2023 (Friday) 15:00-16:00

Organizer:

Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: September 14th

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Stratus HLS (High Level Synthesis) Seminar Series: [Part 1] Let’s learn the basics of high-level synthesis

Stratus HLS (High Level Synthesis) Seminar Series: [Part 1] Let’s learn the basics of high-level synthesis
by Admin on 07-25-2023 at 3:01 pm

Date: August 31, 2023 (Thursday) 15:00-16:00

Organizer: Cadence Design Systems Japan, Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: Wednesday, August

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Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More


Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis

Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis
by Mike Gianfagna on 07-31-2020 at 10:00 am

Screen Shot 2020 07 25 at 2.05.14 PM

There was a “research reviewed” panel on Thursday at DAC entitled Shortening the Wires Between High-Level Synthesis and Logic Synthesis. Chaired by Alric Althoff of Tortuga Logic, the panel explored methods to deal with wire delays in high-level synthesis and logic synthesis. The four speakers and their focus were:

  • Licheng
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From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology

From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology
by Admin on 06-16-2020 at 7:17 am

Register For This Web Seminar

Online – Jul 14, 2020
10:00 AM – 11:00 AM US/Pacific

Overview

Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple

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Mentor Highlights HLS Customer Use in Automotive Applications

Mentor Highlights HLS Customer Use in Automotive Applications
by Bernard Murphy on 07-30-2019 at 6:00 am

Catapult HLS

I’ve talked before about Mentor’s work in high-level synthesis (HLS) and machine learning (ML). An important advantage of HLS in these applications is its ability to very quickly adapt and optimize architecture and verify an implementation to an objective in a highly dynamic domain. Design for automotive applications – for … Read More


Specialized AI Processor IP Design with HLS

Specialized AI Processor IP Design with HLS
by Alex Tan on 01-14-2019 at 12:00 pm

Intelligence as in the term artificial intelligence (AI) involves learning or training, depending on which perspective it is viewed from –and it has many nuances. As the basis of most deep learning methods, neural network based learning algorithms have gained usage traction, when it was shown that training with deep neural network… Read More


Sequential Equivalency Checks in HLS

Sequential Equivalency Checks in HLS
by Alex Tan on 12-13-2018 at 12:00 pm

Higher level synthesis (HLS) of an IP block involves taking its high-level design specification –usually captured in SystemC or C++, synthesizes and generates its RTL equivalent. HLS provides a faster convergence path to design code stability, promotes design reuse and lowers front-end design inception cost.

HLS and MentorRead More