Mentor Highlights HLS Customer Use in Automotive Applications

Mentor Highlights HLS Customer Use in Automotive Applications
by Bernard Murphy on 07-30-2019 at 6:00 am

I’ve talked before about Mentor’s work in high-level synthesis (HLS) and machine learning (ML). An important advantage of HLS in these applications is its ability to very quickly adapt and optimize architecture and verify an implementation to an objective in a highly dynamic domain. Design for automotive applications – for … Read More


Specialized AI Processor IP Design with HLS

Specialized AI Processor IP Design with HLS
by Alex Tan on 01-14-2019 at 12:00 pm

Intelligence as in the term artificial intelligence (AI) involves learning or training, depending on which perspective it is viewed from –and it has many nuances. As the basis of most deep learning methods, neural network based learning algorithms have gained usage traction, when it was shown that training with deep neural network… Read More


Sequential Equivalency Checks in HLS

Sequential Equivalency Checks in HLS
by Alex Tan on 12-13-2018 at 12:00 pm

Higher level synthesis (HLS) of an IP block involves taking its high-level design specification –usually captured in SystemC or C++, synthesizes and generates its RTL equivalent. HLS provides a faster convergence path to design code stability, promotes design reuse and lowers front-end design inception cost.

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Closing Coverage in HLS

Closing Coverage in HLS
by Alex Tan on 10-08-2018 at 12:00 pm

Coverage is a common metric with many manifestation. During the ‘90s, both fault and test coverage were mainstream DFT (Design For Testability) terminologies used to indicate the percentage of a design being observable or tested. Its pervasive use was then spilled over into other design segments such as code coverage, formal… Read More


High-Level Synthesis for Automotive SoCs

High-Level Synthesis for Automotive SoCs
by Mitch Heins on 09-15-2017 at 7:00 am

Some of the world’s most complex Systems-on-Chip (SoCs) are being developed for automotive applications. These SoCs have heterogeneous architectures with a variety of processors and accelerators that do real-time image processing for assisted and autonomous driving applications. The Bosch Visiontec team, in Sophia Antipolis,… Read More


Xilinx is a Software Company

Xilinx is a Software Company
by Paul McLellan on 09-10-2015 at 7:00 am

If you think of Xilinx the word that immediately comes to mind is FPGA. After all they were one of the pioneers of the space. FPGAs are a means of implementing hardware, and the main implementation methodology is RTL-based. This compares to writing software and compiling it for a microprocessor, which is the main software implementation… Read More


High Level Synthesis. Are We There Yet?

High Level Synthesis. Are We There Yet?
by Paul McLellan on 06-16-2015 at 7:00 am

High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More


NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile

NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile
by Daniel Payne on 05-31-2015 at 4:00 pm

Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors… Read More


Shorten the Learning Curve for High Level Synthesis

Shorten the Learning Curve for High Level Synthesis
by Daniel Payne on 01-27-2015 at 4:30 pm

When chip designers moved from a gate-level design methodology to coding with RTL there was a learning curve involved, and the same thing happens when you move from RTL to High Level Synthesis (HLS) using C++ or SystemC coding. One great shortcut to this learning curve is the use of pre-defined library functions. I just heard about… Read More


High Level Synthesis update from #51DAC

High Level Synthesis update from #51DAC
by Daniel Payne on 06-27-2014 at 8:00 pm

Every since Synopsys dominated the logic synthesis market in the 1980’s we’ve had something called HLS – High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DACthis year I met with Mark Milligan of Calypto to get an update on what’s new with HLS. I first… Read More