I really enjoy ARM Techcon when it rolls around every year because it has such a wide range of topics and exhibits. You can find maker gadgets, IoT information, small boards for industrial control, software development kits, semiconductor IP vendors as well as the big EDA players and foundries. This year after perusing the exhibit floor I attended a talk sponsored by Cadence on the topic of using Globalfoundries 22NM FD-SOI process to implement a quad core ARM Cortex-A17. Joerg Winkler and Tamer Ragheb with Globalfoundries discussed the rational for choosing their 22FDX technology for this project. After which, they went into to the specifics of using Cadence Innovus for the actual physical design process. We all know that the 28nm node is popular because of its relatively low cost and ease of implementation. To reduce power or increase performance beyond this companies typically need to make the leap to FinFET nodes, which comes with a big increase in cost and complexity. FD-SOI is increasingly becoming a choice to explore for companies that are looking for lower power and better performance. FD-SOI is already a low leakage process because the of the depleted channel that is insulated from the body silicon. One of the most interesting and appealing aspects of FD-SOI is the ability to dynamically add forward or reverse body bias to the devices without causing more leakage effects. Adding body bias on FD-SOI does not draw current through the source or drain. Forward body bias (FBB) can reduce the voltage needed to cause the gate to switch and also causes a faster transition. Both of these behaviors save significant power and boost performance. Adding reverse bulk bias (RBB) can reduce leakage and is useful for reducing static power consumption when the gates are not needed. The Globalfoundries presentation at ARM Techcon discussed using their unique 22FD-SOI node, which is comparable to 28nm bulk in price, but offers better power/performance when FBB and RBB are designed in. Albeit, extra work is required and their presentation discusses in some detail how the body biasing domains were partitioned and routed. However, the work is comparable to the effort required for power and voltage domains, which are in widespread use. The Cadence Innovus reference flow that was used for the paper is shown below. Globalfoundries has also implemented an ARM Cortex-A9 Neon in a number of different processes for the purposes of comparing PPA. Again the implementations have been done using Cadence Innovus. The 28nm implementation has a single operating point, i.e nominal frequency and total power. Due to the body bias capabilities the 22FDX design can operate over a range of frequencies and corresponding power values. The following chart shows the results. The 22FDX design was implemented twice, with LVT for the FBB case and with RVT for the RBB case, this afforded overlap in their operating ranges. The 22FDX designs are a win any way you look at it. The area is lower and it does better with power and performance, depending which way the body bias is applied. I remember back when low Vt cells were introduced during the time when leakage was starting to grow rapidly relative to dynamic power. Back then I worked with several companies to devise methods for selectively placing high and low Vt cells to squeeze out performance and yet keep the low Vt cell count to a minimum. A solution like 22FDX with body biasing would have been a revelation. 22FDX is like getting a knob to tune the design after it is completed. It’s good that companies are getting more attractive choices for keeping design and fabrication costs low and also improving PPA.
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