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Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect

Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect
by Mike Gianfagna on 02-26-2020 at 10:00 am

At DesignCon 2020, ANSYS held a series of sponsored presentations. I was able to attend a couple of them.  These were excellent events with the material delivered by talented and high-energy speakers. The DesignCon technical program has many dimensions beyond the conference tracks. One of the presentations dealt with 3D ICs. It was presented by Professor Sung-Kyu Lim from the School of Electrical and Computer Engineering at the Georgia Institute of Technology.

The work presented by Professor Lim is funded by DARPA, Arm and ANSYS. I should also point out Professor Lim’s student, Lingjun Zhu contributed to this work as well. The discussion focused on thermal, IR-drop and PPA analysis of 3D ICs built with Arm A7 and A53 processors. Since 3D IC can mean many things, Professor Lim’s focus was on bare die stacking. He reviewed several designs using these techniques from companies such as GLOBALFOUNDRIES, Intel and TSMC.

First, a bit about the design flow used for these test cases. Professor Lim took a practical approach here, adapting commercially available 2D IC design tools to a 3D design problem. Logic/memory designs were decomposed into two tiers, one for logic and one for memory. First, the memory tier was designed, resulting in a pinout for that tier. Then a double metal stack was created. This allowed the memory tier and the logic tier to communicate through dense connections using TSVs, face-to-face pads, or monolithic inter-tier vias (MIVs). Next, the logic tier was placed and routed along with connections from the memory tier that were also represented in the logic tier.

The results of this approach were discussed for an Arm Cortex A7 design, containing L1, L2 cache and logic.  All of the L2 and some of the L1 cache were placed on the memory tier and the rest of the design was implemented on the logic tier. Interconnect between the cache and logic was shortened quite a bit as a result of this approach. A similar process was applied to a Cortex A53 design. See below.

Cortex designs 2D vs. 3D

The results of these experiments yielded a smaller footprint thanks to the two-tier approach and a performance improvement thanks to the shorter routes. In turn, this resulted in more power, higher IR-drop and increased temperature, thanks to the faster operating speed. The results are summarized below.

2D vs. 3D results comparison

Experiments were run on power savings as well.  In this case an LDPC error correction circuit was used. Due to shorter wire lengths and smaller capacitors, a 39% power saving was achieved, illustrating another advantage of 3D design.

Going back to the Arm designs, below are heat maps of the various experiments between 2D and 3D to facilitate thermal comparisons.

2D vs. 3D heat maps

Professor Lim then discussed the tool flow used for these analyses. ANSYS RedHawk was used extensively to perform many tasks, including power, thermal and IR-drop analysis. All of this work was based on very fine-grained analysis of each routing segment and device across many temperature profiles. Below is an overview of the flow.

Design flow

Professor Lim concluded his talk with a discussion about the impact thermal awareness could have on IC design.  He proposed a temperature-aware timing closure flow that would update circuit performance based on actual temperature gradients, which can now be calculated. This approach could produce designs that are much more robust in real-world environments. Below is an overview of the proposed flow.

Temperature aware timing closure flow

To learn more about thermal-induced reliability challenges and solutions for advanced IC designs,please check out this recent ANSYS webinar.

 

 

 


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