WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 34
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 34
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
    [is_post] => 1
)

Concept Engineering Showcases Effective SoC Debugging Techniques

Concept Engineering Showcases Effective SoC Debugging Techniques
by Pawan Fangaria on 05-15-2014 at 10:00 pm

In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization of the overall design in terms of timing, power and area is of utmost importance. Often designers find it difficult to correlate the design at the RTL, gate, transistor and RC levels; debugging at parasitic level becomes very cumbersome. Imagine looking at the RC network of a net in the sea of a million gate circuit! One needs easy and user friendly tools to quickly isolate, comprehend and analyze particular portions or components of a design in order to inspect and debug them properly.

After attending some of the demos and webinars of Concept Engineering, I can confidently say that they have a class of really effective tools which allow designers to easily comprehend and focus on any portion of interest in their design to debug and optimize the design. The tools can show any component or group of components at the lowest level of transistor along with R and C as well as at the highest level of abstraction for simplicity with a great navigation capability that keeps the things in sync and demarcated as needed by the user. The tools can be used with great level of ease and flexibility at pre-layout as well as at post-layout stages.

It’s pleasing to say that Concept Engineering is showcasing their offerings at DAC 2014. There will be presentations and demos on various tools, solutions, debugging methods & tips throughout the days on June 2-4. Concept Engineering has tools at all levels – StarVision which works at all levels for SoC debugging and IP integration, RTLvision, GateVision and SpiceVision. Also they provide software components for EDA tool developers for them to integrate these capabilities in their environment. NIview is a schematic generation utility which has an option for added GUI that can be based on Qt, Java, Tcl/TK, Perl/TK, MFC and so on as needed by the EDA tool vendor; there is a provision not to have GUI as well, in which case NIview works for schematic generation in batch mode. Also, Concept Engineering provides powerful customization to EDA and design tools through several user ware APIs which they ship with complete documentation that can help users to even develop new APIs at their end as well.

It’s an opportunity for those who are attending DAC to visit Concept Engineering booth #1201 and see their tools & technologies live to get an actual feel of how effectively they can help in SoC design, debug and optimization and IP integration. A deep dive discussion can be arranged on request for specific design needs or tool customizations.

By using Concept Engineering tools, one can view a design at any desired level – RTL, Gate or Spice, instantaneously on-the-fly; there can be mixed-signal and mixed-language level viewing as well along with cross-probing between different views. A fragment of the circuit can be extracted and saved as Spice netlist which can be externally used for partial simulation and re-use in IPs. The parasitic structures can be turned off for easy recognition of CMOS functions in a complex circuit. A logic symbol and schematic can be automatically created from a Spice netlist. The post-layout parasitic networks (DSPF, RSPF or SPEF) can be visualized and analyzed, and Spice netlists can be created for critical path simulation and analysis. The parasitics can be back-annotated at pre-layout stages. During tape-out time when there is a need of fast debugging, selected elements can be dragged and dropped between different views such as schematic, cone, parasitic and source code and cross probed. Cone views can be used very effectively for AMS design debugging because they provide very clear picture of tracing signals passing through different levels of hierarchies. The Clock Tree Analyzer in StarVision provides a graphical representation of all clock domains along with their interconnections. A double click at any interconnection can show the clock domain crossing in that path. The tool has an integrated waveform viewing capability. The connectivity checking (ERC) can be done to identify any floating or incomplete nets or components. The structures such as multi fan-in and fan-out can be checked for heavy load or drive.

The list of techniques and features in these tools is never complete without actually seeing and experiencing them. Whenever I have seen these tools, either in a demo or in a webinar presentation, I found new features and new ways of operations in these tools. They are extremely versatile, flexible and fast which can easily delight their users!

It will be a very positive experience visiting booth #1201, Moscone Center at the 51[SUP]st[/SUP] DAC on June 2 – 4, 2014.

More Articles by Pawan Fangaria…..

lang: en_US


0 Replies to “Concept Engineering Showcases Effective SoC Debugging Techniques”

You must register or log in to view/post comments.