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Debugging a 10 bit SAR ADC

Debugging a 10 bit SAR ADC
by Daniel Payne on 10-31-2014 at 4:00 pm

SMIC (Semiconductor Manufacturing International Corporation) is a China-based foundry with technology ranging from 0.35 micron to 28 nm, and we’ve blogged about them before on SemiWiki. I’ve been reading about SMIC recently because they created a technical presentation for the MunEDA Technical Forum Shanghai in March. They will also present this at the MunEDA User Group meetingon Nov 17-18 in Munich, Germanywith the title: SAR ADC Debug Using WiCkeD. The acronym SAR ADC means Successive Approximation Register, Analog to Digital Converter. These converter circuits accept an analog input, then create a precise digital value output at a certain sampling rate and resolution of bits. Other types of converter architectures are: pipeline, flash and sigma-delta ADCs.

Simplified N-bit SAR ADC Architecture

A customer design fabricated at SMIC in 40 nm technology contained a 10 bit SAR ADC with low performance yield, so SMIC engineers set about to debug the source of the low yield and improve it. The ADC was producing wrong code conversion values and only reached an Effective Number Of Bits (ENOB) of 6, instead of the intended 10. Running a full SNDR (Signal to Noise plus Distortion Ratio) simulation on this circuit with 3,500 devices required tens of hours, so was not deemed efficient for debug purposes.

Low performance yield with ENOB of 6, instead of 10

Related – Transistor-level Sizing Optimization

To debug this low yield issue they used an EDA tool from MunEDA called WiCkeD where the debug flow is based upon using a fail pattern and testbench:

Differential Nonlinearity (DNL) error is defined as the difference between an actual step width and the ideal value of 1 LSB (Least Significant Bit).

DNL must be less than 1 LSB for no missing codes

Next, a large number of key devices were selected to see how they impacted deviation values while varying values of Vin. Results from the key devices finding showed that devices in the capacitor array had the greatest impact on deviation, followed by devices in the second stage comparator, and finally devices in the first stage comparator.

Mismatch analysis was run on sub-blocks independently to identify sensitive blocks before analyzing single devices. This hierarchical approach greatly reduces the simulation effort.

Related – An IO Design Optimization Flow for Reliability in 28 nm CMOS

Plots were made to show the distortion behavior of each device to see if correlation was negative or positive:

Device variation, the deviation value for code 496 caused by distortion is negative correlated

Device variation, the deviation value for code 504 caused by distortion is positive correlated

While verifying the size parameters and process parameters it was found that the MOM (Metal Oxide Metal) capacitor’s mismatch was the main cause of distortion. So by changing the mismatch variation in the MOM capacitor the simulated value for ENOB improves from 6 (Red) to 9 (Green):

ENOB improvement by modifying the mismatch variation of MOM capacitor


A 10 bit SAR ADC with low yield was debugged using the WiCkeD tool to pinpoint the source of deviations. Reducing the mismatch variation of MOM capacitors in simulation increased ENOB significantly, proving that the issue was actually caused by the local variation of these devices. The SMIC debug strategy was based on the designer’s circuit knowledge, and enabled by MunEDA’s flexible, interactive analysis tools.

To view the 19 page presentation by SMIC, request it online.

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