When Design Gets Faster, the Bottleneck Moves Through the Physical Stack

When Design Gets Faster, the Bottleneck Moves Through the Physical Stack
by Moh Kolb on 09-07-2026 at 6:00 am

Desing fast Bott through physicalstack

AI can compress the path to tape-out. The next challenge is compressing physical realization.

Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.

AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More


Webinar: Avestra – Assertion Driven Silicon Success

Webinar: Avestra – Assertion Driven Silicon Success
by Admin on 09-02-2026 at 2:36 am

COMPANY EMAIL REQUIRED FOR REGISTRATION.

Studies show that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration — work that remains largely manual today or is delegated to general-purpose LLMs that hallucinate more than 30% of the time and produce incorrect assertions.… Read More


Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance

Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance
by Admin on 08-25-2026 at 2:00 pm

Intel Wildcat Hot Chips 2026

Lance Hacking, Intel

Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More


Europe OIP Ecosystem Workshop

Europe OIP Ecosystem Workshop
by Admin on 08-24-2026 at 12:15 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


Japan OIP Ecosystem Workshop

Japan OIP Ecosystem Workshop
by Admin on 08-24-2026 at 12:06 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


TSMC 2026 North America OIP Ecosystem Forum

TSMC 2026 North America OIP Ecosystem Forum
by Admin on 08-24-2026 at 12:04 am

Join Us to Connect, Collaborate, and Shape the Future of AI

Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event—it’s the ultimate collaborative hub where the world’s leading technology pioneers gather to discuss… Read More


Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)

Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)
by Moh Kolb on 05-19-2026 at 8:00 am

PictureGFL

The semiconductor industry has achieved extraordinary mastery in silicon signoff. Modern EDA environments can now optimize timing closure, physical verification, IR/EM behavior, routing density, thermal interaction, and increasingly even design-space exploration through AI-assisted implementation flows. Crossing… Read More


Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers

Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers
by Daniel Nenni on 03-10-2026 at 8:00 am

CAE INL 2025

Mid-infrared (MIR) photonic integrated circuits are emerging as a key technology for applications ranging from environmental monitoring and medical diagnostics to defense and industrial process control. The MIR spectral region, often referred to as the molecular “fingerprint” region, exhibits strong absorption features… Read More