One of the more frequent questions I get, “What is next after FinFETs?” is finally getting answered. Thankfully I am surrounded by experts in the process technology field including Scotten Jones of IC Knowledge. I am also surrounded by design enablement experts so I really am the man in the middle which brings us to a discussion between Rod Metcalfe, product management group director in theDigital & Signoff Group at Cadence, Peter Debacker R&D team leader at imec, and SemiWiki on the 3nm testchip announcement.
Semiwiki questions for imec and Cadence:
Semiwiki readers are very interested in process technology scaling and EDA methodologies. These questions probe into additional details, beyond the recent press release:
The press release mentions “FinFET process node requirements”. Also, imec recently announced significant progress on a horizontal gate-all-around process.
- What device type(s) have been developed for 3nm? (e.g., FinFET, GAA, other?)
- What unique device materials are being employed? (e.g., new stressors, SiGe substrate, gate oxide EOT)
- What VDD_nom is assumed?
- What Vt options are available?
- How do leakage currents and body effect compare to previous nodes?
- Is an Ion_versus_Ioff curve available?
For 3nm, we consider low track height standard cells down to 4.5T. These will only be able to fit a single fin or a single lateral nanosheet per device. In order to meet power and performance requirements for these high density standard cells, the nanosheets will be crucial, as a single fin device can only be boosted so much.
For device-specific questions, we cannot disclose additional details vs what was published at VLSI 2017. There is a pretty thorough summary at IEDM 2017 – imec Charting the Future of Logic on SemiWiki.
The test chip was designed using high-density single fin 4.5T standard cells
Additional Fabrication Updates:
– What metallurgy is used for MEOL metals, contacts? With an aggressively scaled metal pitch, what damascene trench cladding and fill metal(s) are used?
One of the main goals of this test chip was to evaluate various BEOL and MEOL processes and evaluate the impact on wire RC, variability, reliability etc. We will look beyond the standard dual damascene Cu process and look at various Ruthenium based options as possible replacements
– The press release mentions a TRIM metal flow – is this a distinct method from existing metal trim lithography?
This is not fundamentally different, but, of course is extra challenging to realize at a 21nm metal pitch. We used a self-aligned TRIM process for the metal patterning.
-The press release mentions “193i versus EUV” experiments – what layers were evaluated using these exposure alternatives? What multipatterning strategies were needed? What were the CD overlay targets?
Our high-level lithography view on N5 and beyond was covered in the recent SPIE invited paper:
“Imec N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend (Invited Paper), Ryan Ryoung-Han Kim, Syed Muhammad Yasser Sherazi, Peter Debacker, Praveen Raghavan, Julien Ryckaert, Arindam Malik, Diederik Verkest, Jae Uk Lee, Werner Gillijns, Ling Ee Tan, Victor Blanco, Kurt Ronse, Greg McIntyre, IMEC (Belgium). . . . . . . . . . . . . . . . . . . . . . [10588-22]- https://www.spiedigitallibrary.org/conference-proceedings-of-spie/10588/105880N/IMEC-N7-N5-and-beyond–DTCO-STCO-and-EUV/10.1117/12.2299335.full?SSO=1
A more detailed view on metal patterning for a 21nm pitch is covered in this SPIE 18 paper: https://www.spiedigitallibrary.org/conference-proceedings-of-spie/10589/105890E/Exploration-of-BEOL-line-space-patterning-options-at-12-nm/10.1117/12.2297183.full
The test chip’s main goal is to cover a 21nm pitch line and via patterns. 193i SAQP as well as multiple patterning EUV can be used for these pitches. Both via masks and metal block masks will be the first candidates for EUV as this can drastically reduce mask count (and, hence, cost) for vias and blocks vs immersion-based lithography.
– What design latitude is available? What design options are available for gate length? For metal widths (e.g., 1X, 1.5X, 2X)?
The test chip offers a limited set of metal pitches, where the tightest pitch (and the one the whole test chip was set up to test for) is 21nm.
– The press release mentions that “metal interconnect variation would be measured and improved” – is there additional detail available about the process control steps taken to address metal linewidth variation?
We cannot disclose the specific methods used.
– What SRAM cell design(s) were included in the 64-bit processor testchip? (Are multiple bit cells available, for high performance and high density?) What is the VDD_min target for the SRAM arrays?
There is a separate SRAM-based test structure, but it is not integrated with the processor. The processor is logic, high-density cells only.
– What standard cell design style was used?
– cell height in # of tracks
– maximum # of (nFET and pFET) fins in the cell height
– cell library Vt and drive strength options
– maximum series device stack height in the logic library
– P/G rail design in the cell image, to handle the local current density
– cell adjacency design style (e.g., cells abutted with tie-off gate, or cells separated by dummy devices)
See https://www.spiedigitallibrary.org/conference-proceedings-of-spie/10588/1058809/Track-height-reduction-for-standard-cell-in-below-5nm-node/10.1117/12.2297191.full for imec’s view on the details of standard cells for 3nm. For this test chip, we used high-density 4.5T cells, 1fin cells, LVT only, one L only, with a 2 CD power rail and a full PDN included. We did not do IR drop or full timing closure, as this is an early 3nm test chip focusing on the BEOL exploration.
– Additional circuit design features? (e.g., triple-well device option; ESD design; thermsense macro; analog circuit R and C elements)
The test chip additionally features a range of BEOL test structures to assess yield, variability of various BEOL process options under consideration for 3nm
– What I/O circuit types were used? (e.g., thicker tox, longer Lg, higher VDDIO)
None, no specific IO test circuits were implemented.
What EDA flows were impacted?
– custom parasitic extraction (new layout-dependent effects?) / suitability of existing BSIM-CMG definition for compact device modeling?
Imec has its own BSIM-CMG based macro-model built around the standard BSIM-CMG and extended with an imec proprietary parasitics model.
– cell characterization (new corner definitions?)
As the test chip’s goal is mainly to characterize the BEOL for various process options, we did not put focus on the cell characterization flow.
– self-heating and electromigration analysis?
While self-heating and electromigration modeling and mitigation will be certainly crucial in final product designs, this test chip did not use specific EDA flows. Instead the test chip will have specific test structures to evaluate reliability effects and the impact of self-heating.
-What new Genus and Innovus tool features were required to support the 3nm testchip?
- physical synthesis cell optimizations for PPA?
- routing support for advanced multipatterning?
- routing optimizations for PPA, multipatterning, and noise avoidance (in support of TRIM)
- any new DRC (or ERC) algorithms for PVS? new fill insertion algorithms? any other new DFM features required?
The testchip implemented logic from a 64-bit CPU using 3nm standard cells created by imec. The Cadence Genus Synthesis Solution was used for RTL synthesis, and the Innovus Implementation System for implementation. A 3nm technology file was jointly created by imec and Cadence which defined the 21nm routing pitch, and additional rules required for the 3nm process node. Using the Cadence tools, 3nm technology file, and imec standard cell library, a design rule correct GDS file was created, which was then used for the testchip.