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Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and quick visualization, navigation, annotations etc. are a must for designers to make right decisions during the course of design. The designers should be able to easily analyze different parts of the design which can be in different languages such as Spice, Verilog, VHDL, SystemVerilog etc. and can have different levels of voltages and signals.

Last week I attended a webinaron Mixed Signal SoC Verification hosted by EDA Directwhere they showcased StarVision[SUP]TM[/SUP]tool from Concept Engineeringthat does the job quite elegantly at all levels. Lokesh Akkipeddi of EDA Direct presented interesting capabilities of StarVision[SUP]TM[/SUP] followed by a demonstration. While the video shoot of the webinar can be available in future, I wanted to highlight some of the key capabilities of the tool which appeared very apt for quick and easy debugging of typical scenarios in SoCs, which can otherwise be very cumbersome and time consuming. That enables designers to easily and effectively integrate IPs into an SoC.

The overall semiconductor design can be visualized with its parts at Spice, Gate or RTL level either in schematic or in its source code format. Post layout and netlist interfaces can be easily represented and visualized. Hence any third party IP in available format can be quickly imported into the flexible GUI and then analysed, debugged and integrated into the SoC.

A quick and easy way is to use cone view for debugging AMS designs; cone views provide very clear picture for tracing signals passing through different levels of hierarchy in the design.

In large SoCs, there can be several clocks driving various parts of the overall semiconductor design. It’s very important to check if there is any clock domain crossing issue. The Clock Tree Analyzer in StarVision[SUP]TM[/SUP] presents all clock domains and their interconnections in an easy to view graphical form. By double clicking on any interconnection, designers can view the clock domain crossing in that path.

Timing closure is a major concern in SoC verification; violations need to be appropriately understood before fixing them. StarVision[SUP]TM[/SUP]automatically annotates schematics with timing information from PrimeTime report. Timing violations on any circuit element can be easily spotted and appropriate action taken.


There is an integrated waveform viewer which can show the complete waveform from VCD data. StarVision[SUP]TM[/SUP]also annotates source and cone views with the VCD data as appropriate. The toggling nets at various components in the cone view and the source view are clearly visualized for the designers to get a feel of consistency in functioning of the circuit as desired.

Although there is provision to visualize the circuit with complete parasitics, to recognize a particular circuit with ease, there is provision to hide parasitics and simply view the circuit with only logic components. For recognizing circuits, there are other features as well such as merging of parallel transistors. Again there is provision to view logic symbols as per desired library such as Cadence. In this example circuit, it’s very difficult to recognize the inverter in the RC view which has all resistances and capacitances cluttered along with the transistor symbols. However that is clearly recognized in non-RC view.

It’s very tedious work to do post layout parasitic level analysis. However it’s very important to be able to fix issues at this stage without disturbing the whole circuit and initiating a whole iteration of the costly design flow. StarVision[SUP]TM[/SUP]provides an easy-to-use drag & drop of nets which can be viewed in full parasitic format with the data read from SPEF or DSPF file. Multiple nets can be viewed at a time in different colors.

Overall it was a great session with live interaction with Lokesh. Look for more information about this product or webinar at EDA Direct here. A self-running demo of StarVision[SUP]TM[/SUP]is also available at Concept Engineering website here.

More Articles by Pawan Fangaria…..

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