Static Timing Analysis Keeps Pace with FinFET

Static Timing Analysis Keeps Pace with FinFET
by Daniel Payne on 04-22-2016 at 12:00 pm

At SemiWiki we’ve been blogging for several years now on the semiconductor design challenges of FinFET technology and how it requires new software approaches to help chip designers answer fundamental questions about timing, power, area and design closure. When you mention the phrase Static Timing Analysis (STA) probably… Read More


Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly.… Read More


Schematic, IC Layout, Clock and Timing Closure from ICScape

Schematic, IC Layout, Clock and Timing Closure from ICScape
by Daniel Payne on 06-08-2012 at 11:10 am

Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.

Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)

ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun… Read More


Timing Closure for ECOs in your SOC Design

Timing Closure for ECOs in your SOC Design
by Daniel Payne on 03-14-2012 at 1:07 pm

I decided to attend a webinar today hosted by Synopsys, “Streamline Your PrimeTime ECO Flow For Fastest Setup, Hold and Timing DRC Closure.” The format was to present slides first then hold for questions until the end. Enough time was spent on questions which made this webinar different than most other webinars I’ve… Read More