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Global Variation and Its Impact on Time-to-Market for Designs

Global Variation and Its Impact on Time-to-Market for Designs
by umangdoshi on 04-14-2021 at 2:00 pm

We have come a long way from the days of limited and manageable characterization databases with fewer views and smaller library sizes. The technologies we are headed towards pushing characterization to its limits with special modeling for variation, aging and reliability all on a single process, voltage and temperature (PVT). Additionally there is a requirement to generate basic nominal timing/noise/power views as well as more complex variation views.

With the advancement in technology and the push towards smaller nodes from 7nm down to 3nm, the designs are expected to work under different modes, with possibly different clock frequencies along with a range of global variations. Thus, the designs have to achieve signoff closure for timing and power across an enormous number of PVT corners. Characterizing these huge number of PVT corners, library teams across the industry face further challenges like high simulation turnaround time, database disk-space, license server overloads and hardware costs. All of these result in overall impacting adversely the time-to-market delivery of designs in a cost-effective manner.

Impact of Global Variation on Delay

Characterizing multiple PVT corners can be done using multiple methodologies. One such is brute-force method, where using many compute resources runs all possible PVT corners required in parallel and thus reduces the overall turn-around time (TAT). Another method is to characterize timing data for nominal while scaling the Liberty Variation Format (LVF) data, which is about 60-70% of the overall runtime for library characterization, thus achieving 2-4X faster TAT. Both these methods have their pros and cons -while the compute cost to generate all libraries in parallel is significantly higher, the libraries are very accurate, whereas for scaled LVF data the compute cost is lower, but with a possible sacrifice in accuracy.

SmartLVF methodology

Not only does Synopsys offer a feature for scaling LVF data to generate SmartLVF (as illustrated in Figure 2) libraries for multiple PVT corners, we have developed an advanced ML-based scaling feature called SmartScaling which fits right into this requirement space to provide the much-required relief for designers. SmartScaling for multi-PVT characterization enables designers to create interpolated Liberty models at zero cost while maintaining signoff accuracy. This significantly reduces overall runtime and alleviates concerns of database management thus providing the most accurate, cost-efficient solution.

With an easy-to-use UI to accept user-defined anchor libraries over a range of conditions, SmartScaling can quickly create libraries at other corners as chosen by the user. While this is the most basic usage, it also offers further advantages to adaptively select anchor corners to get best scaling accuracy, accept user-controlled custom indices, do some cross-PVT trend checks and then some more!

SmartScaling Multi-PVT methodology

Designer’s needs may vary – from simply creating structurally consistent placeholder Libs for end- to-end flow flush to producing accurate intermediate PVT’s for signoff – and the solution is SmartScaling.

Summary

Multi-PVT characterization has become necessary to generate libraries that include model variations, aging and reliability data at the most advanced nodes. This imposes an increased demand for computing resources needed for characterization which increases time-to-market and overall cost for the design. Synopsys’s SmartScaling for multi-PVT characterization improves the runtime significantly to provide over 3X increase in efficiency and reduce overall cost.

With latest innovation in Synopsys’s library characterization, achieve faster and more accurate variation models with the goal of generating PrimeTime® signoff quality libraries. Learn more about the close collaboration and integration between various signoff products at www.synopsys.com/signoff

Also Read:

VC Formal SIG Virtually Conferences in Europe

Key Requirements for Effective SoC Verification Management

Techniques and Tools for Accelerating Low Power Design Simulations

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