What Makes A Designer’s Day? A Bottleneck Solved!

In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out time, when the actual layout is ready, every day spent in debugging and resolving issues feels like climbing one large peak of the mountain. And in a semiconductor design, the actual proof of design becomes available only with actual layout when actual parasitic elements like resistances and capacitances often dominate the design performance. Fixing the parasitic issues at that stage is a burgeoning and time consuming task as fixing at one place can lead to side effects at other places in the overall design.

An efficient methodology and tools to quickly analyse and fix these issues can be a boon for designers. I’m pleased to see this webinar on Parasitic Debugging made easyon 11[SUP]th[/SUP] Dec, organized by Concept Engineering that provides a great amount of detail about their tools and methodologies to quickly debug parasitic effects under various contexts. I believe this can make designers job a lot easier to analyse and fix issues post layout.

What I see from the postings on their website is – several capabilities at the schematic and SPICE netlist level which can efficiently and effectively be used with ease to analyse, debug, re-arrange and visualize different parts of a design, and also integrate the design with other designs which may have been developed by using other industry standard EDA tools.

Parasitic networks (can be in any format such as SPEF, DSPF or RSPF) can be analysed and SPICE netlists created for critical path simulation. In the SPICE circuit, identified parasitic structures can be turned ON and OFF for better understanding of CMOS function.

Important parts of the circuit can be navigated, extracted and saved as SPICE netlist that can be further re-used as IP or other external use. Schematics can be rendered on-the-fly for SPICE level netlists to easily understand the functioning of the circuit.

The design environment supports ‘Drag & Drop’ of selected elements between all design views including source code, parasitic window, logic cone and schematic. This provides a finer quicker cross probing and debugging.

Other features to complete the design environment include automatic creation of symbols and schematics from SPICE netlists, ERC checking and debugging, export of schematics into Cadence Virtuosoand compatibility of SPICE support with its variations and different simulation tools across the semiconductor design industry.

Another important item to be discussed is – how to extend SpiceVision (Concept Engineering’s interactive visualization tool for analysing and debugging SPICE models and circuits) functionality, according to project needs, by interfacing with the open database through TCL scripts.

A detailed notice about the program of the webinar is posted on semiwiki website here. It’s a one hour free webinar on 11[SUP]th[/SUP] Dec and that one hour is worth spending to gain the valuable insight into how to avoid wastage of time and utilize it productively in fixing crucial parasitic issues post layout.

Register Here Happy attending!!

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