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What does 3D IC, FinFETs, and EUV have in common?

What does 3D IC, FinFETs, and EUV have in common?
by Daniel Nenni on 06-19-2013 at 6:00 pm


They are three of the top trending terms on SemiWiki and three of the hot topics at this year’s Semicon West:

In its 43rd year, SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

The semiconductor ecosystem is showcased at SEMICON West with over 50 hours of technical programs and 600+ exhibitors. To see what’s new check out theSilicon Innovation Forum which brings together new and emerging companies with the semiconductor industry’s top strategic investors and leading technology partners. Paul McLellan and I will be blogging live from SEMICON West this year so stay tuned to SemiWiki if you can’t make it.

3D IC: What the leaders are saying about the techniques, technologies, trends and applications for stacked chips

[TABLE] style=”width: 579px”
|-
| colspan=”2″ style=”width: 25%” | Tuesday, July 9, 2013
|-
| valign=”top” style=”width: 25%” | 10:30am-12:30pm

| Generation Mobile: Enabled by IC Packaging Technologies
Hosted by the Advanced Packaging Committee, SEMI Americas TechXPOT North, North Hall
|-
| style=”width: 25%” |

|

|-
| valign=”top” style=”width: 25%” | 1:30pm-4:45pm

| IEEE/CPMT Workshop on:“THIN IS IN”: Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era
San Francisco Marriott Marquis
|-
| style=”width: 25%” |
|
|-
| colspan=”2″ style=”width: 25%” | Wednesday, July 10, 2013
|-
| valign=”top” style=”width: 25%” | 1:00pm-3:30pm
| Advancing 2.5D and 3D Packaging through Value Engineering
Hosted by the Advanced Packaging Committee, SEMI AmericasTechXPOT North, North Hall
|-
| style=”width: 25%” |
|
|-
| colspan=”2″ style=”width: 25%” | Thursday, July 11, 2013
|-
| valign=”top” style=”width: 25%” | 10:30am-1:00pm
| MEMS & Sensor Packaging for the Internet of Things
Hosted by the Advanced Packaging Committee, SEMI AmericasTechXPOT North, North Hall
|-
| style=”width: 25%” |
|
|-
| valign=”top” style=”width: 25%” | 1:30pm-3:35pm
| ITRS Back End of Line Technologies (Partner Event)
TechXPOT North, North Hall

|-

Leveraging Nonplanar Transistor Architectures and New Materials
to Power Mobility Apps Beyond 20nm

Tuesday, July 9, 2013
10:30am–12:30pm
South Hall, Moscone Center

[TABLE] style=”width: 100%”
|-
| colspan=”3″ valign=”top” style=”width: 10%” |
|-
| colspan=”3″ valign=”top” style=”width: 10%” | The mobile market is driving the semiconductor industry to continue its move to transistor architectures that offer greater performance and power benefits than traditional planar architectures. There is not, however, only one way to achieve the required performance. IC manufacturers are pursuing different strategies including leveraging innovations in design rules. To continue the pace of development below 20nm, however, the industry will need to find suitable new channel materials and processes (e.g., MOCVD). This session will present various transistor architecture options below 20nm and the status of channel materials development. Additionally, inspection and metrology challenges associated with new materials will be discussed.
|-
| valign=”top” |
|
|
|-

[TABLE]
|-
| valign=”top” style=”width: 22%” | 10:30am-10:50am
| valign=”top” style=”width: 20%” |
| valign=”top” | Main Features and Benefits of 14nm Ultra Thin Body and BOX(UTBB) Fully Depleted SOI (FD-SOI) Technology

Michel Haond(Biography)
FD-SOI Technology Director
STMicroelectronics

|-
|
|

|

|-
| valign=”top” | 10:50am-11:10am
| valign=”top” |
| valign=”top” | Enabling SoC Level Differentiation Through Advanced
Technology R&D


Subramani Kengeri (Biography)

Vice President, Advanced Technology Architecture, Office of the CTO
GLOBALFOUNDRIES
|-
|
|

|

|-
| valign=”top” | 11:10am-11:30am
|

| Meeting the Challenges of Next-Generation Scaling

George Gomba
VP, Semiconductor Process R&D
IBM

|-
|
|

|

|-
| valign=”top” | 11:30am-11:50am
|
| Non-Silicon R&D Challenges and Opportunities

Paul Kirsch, Ph.D. (Biography)
Director, Front End Processes
SEMATECH
|-
|
|

|

|-
| valign=”top” | 11:50am-12:10pm
|
| valign=”top” | Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm

Adam Brand
(Biography)

Director, Transistor Technology Group
Applied Materials
|-
| valign=”top” |
|

|
|-
| valign=”top” | 12:10pm-12:30pm
|
| valign=”top” | New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology

Joe Sawicki (Biography)
Vice President and General Manager, Design-to-Silicon Division
Mentor Graphics

|-
| valign=”top” |

|

|
|-
| valign=”top” | Session Moderator:
| colspan=”2″ | Debra Vogler (Biography)
President, Instant Insight

|-

Still a Tale of Two Paths: Multi-patterning Lithography at 20nm and Below:
EUVL Source and Infrastructure Progress


Wednesday, July 10, 2013
10:30am–12:35pm
South Hall, Moscone Center

[TABLE] style=”width: 100%”
|-
| style=”width: 25%” |

|
|
|-
| colspan=”3″ style=”width: 10%” | DescriptionThough progress to take EUVL into the realm of high-volume manufacturing continues to be made, the readiness of the source technologies to take on HVM are still not known with a high degree of certainty. The challenges facing source development are still average power, dose stability and uptime. EUV mask and resist infrastructure readiness activities must also come together in time and address such challenges as defect density (for masks), and line edge roughness, sensitivity, and resolution for resists. No doubt, there will be multiple opportunities to insert EUVL into lower volume production lines – such opportunities will be based on specific products and device applications. Until EUVL is ready for HVM, the industry must continue to rely on double-patterning and even multiple-patterning lithography schemes using 193 immersion lithography to take it beyond 22nm. Speakers will present the current status of EUVL readiness, as well as discuss the current plans and challenges of extending 193i with double and multiple-patterning.

|-
|
|
|
|-

[TABLE]
|-
| style=”width: 22%” | 10:30am-10:55am
| style=”width: 22%” |
| ArF Lithography Extension Through Advanced Overlay and Imaging Solutions

Stephen Renwick, Ph.D. (Biography)
Sr. Research Scientist
Nikon Research Corporation of America


|-
|

|

|
|-
| 10:55am-11:20am
|
| EUV Status and Outlook

Stefan Wurm, Ph.D. (Biography)
Director of Lithography

SEMATECH


|-
|

|

|
|-
| 11:30am-11:45am
|

| ASML’s NXE Platform Performance and Volume Introduction

Skip Miller(Biography)
Director of Strategic Marketing
ASML


|-
|

|

|
|-
| 11:45am-12:10pm
|
| Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers

Ben Rathsack, Ph.D. (Biography)

Manager, CLEAN TRACK Advanced Technology Group, Member of Technical Staff for the Semiconductor Production Equipment (SPE) Division

Tokyo Electron America


|-
|

|
|
|-
| 12:10pm-12:35pm
| style=”width: 22%” |
| Collaboration to Deliver Lithography Solutions

Mike Rieger (Biography)
Group Director, R&D, Silicon Engineering Group
Synopsys

|-
|
| style=”width: 22%” |

|

|-
| Session Moderator:
| style=”width: 22%” |
|
Vivek Bakshi (Biography)
Founder and President of EUV Litho, Inc

|-

lang: en_US

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