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SEMICON West: My Top Picks

SEMICON West: My Top Picks
by Paul McLellan on 06-20-2013 at 11:21 am

 I will be at Semicon West from 9th to 11th July in Moscone, San Francisco. Of course there are lots of interesting sessions but here are two that I think are especially important to get a good impression of the way things are going in the future from experts. The two most interesting questions about the future are what comes after 14nm, and is EUV ever going to work for volume manufacturing. These two sessions look at exactly these issues.

On Tuesday 9th from 10.30 to 12.30 in TechXpot South (in the south hall) is Leveraging Non-Planar Transistors and New Materials to Power Mobility Apps Beyond 20nm. The session is actually divided into 6 subsections:

  • Michael Haond, FD-SOI Technology Director for STMicroelectronics on Main Features and Benefits of 14nm Ultra Thin Body and Box (UTBB) FD-SOI Technology. FD-SOI is the alternative to FinFET for getting the channel thin enough to get good control by the gate, and ST is the leading company developing the technology (GlobalFoundries will also have FD-SOI as well as FinFET).
  • Subrmani Kengeri, VP Advanced Technology Architecture of GlobalFoundries, on Enabling SoC Level Differentiation Through Advanced Technology R&D. Global as the #2 foundry has to differentiate itself from TSMC in technology, not just price.
  • George Gomba, VP Semiconductor Process R&D at IBM on Meeting the Challenges of Next Generation Scaling. I always learn a lot listening to IBM talking about the futures of process development. And IBM is in the Common Platform Alliance with Global and Samsung.
  • Paul Kirsch, Director of Front-end Processes at Sematech on Non-silicon R&D Challenges and Opportunities. I’m not sure if he is going to be talking about carbon nanotubes or just germanium, gallium etc.
  • Adam Brand, Director of Transistor Technology Group at Applied Materials on Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm. The FinFET roadmap to 14nm is pretty clear but beyond it is definitely murky.
  • Joe Sawicki, VP Design to Silicon Division of Mentor Graphics on New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology. Since Calibre is the de facto standard for RET, hearing what Mentor has to say about this area is important.

Full details on the session here.

On Wednesday, same time same place, 10.30am to 12.35pm in TechXpot South, is Still a Tale of Two Paths: Multipatterning Lithography at 20nm and Below: EUVL Source and Infrastructure Progress. If you want to know if EUV or DSA are ever going to be real, this is the place to come and find out. I learned a lot at the equivalent session last year.

  • Stephen Renwick, Sr Research Scientist at Nikon on ArF Lithography Extension Through Advanced Overlay and Imaging Solutions.
  • Stefan Wurm, Director of Lithography at Sematach, on EUV Status and Outlook. If anyone knows what is actually happening, he does.
  • Skip Miller, Director of Strategic Marketing at ASML on ASML’s NXE Platform Performance and Volume Introduction. ASML with investments from Intel, TSMC and Samsung is the company developing EUV lithography steppers, light sources etc
  • Ben Rathsack, Manager Clean Track Advanced Technology Group at Tokyo Electron America on Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers. DSA involves mixing non-mixable polymers and having them align themselves into rows or grids. It has gone from an academic research of little practical interest to a serious contender for how we might manufacture below 10nm.
  • Mike Rieger, Group Director of R&D in the Silicon Engineering Group at Synopsys on Collaboration to Deliver Lithography Solutions.

Full details on the session here.

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