ANSYS Enters the League of 10nm Designs with TSMC

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award. Read “ANSYS Tools Shine at FinFET Nodes!”. Just before this Intel also certified ANSYS tools at 14nm Tri-gate process as written in another article, “Intel & ANSYS Enable 14nm Chip Production”. And this week, TSMC has certified ANSYS Power Integrity and Electromigration (EM) solutions for 10nm FinFET process node. It’s amazing progress! Read the press release here.

ANSYS portfolio of products was showcased in the TSMC Technology Symposium held in San Jose, California on 7[SUP]th[/SUP] April, 2015. ANSYS’ RedHawk and Totem were certified by TSMC for 10nm FinFET DRM and Spice models. These tools were certified to provide solutions for static and dynamic voltage drop analysis and advanced signal and power EM verification that are required for ultra-low power and high performance SoC designs at 10nm for mobile, computing and networking applications.

At 10nm process node the devices are left with extremely low noise and reliability margins and FinFET’s structure is typically prone to increasing self-heat.

As shown in the picture, heating happens at the device (FEOL) as well as interconnect (BEOL) levels and hence both need to be considered. At sub-28nm process nodes, as we go down the node, the current density increases and makes the device increasingly vulnerable to EM. In a FinFET the current density can be generally 25% more than that in a planar transistor. Also the narrow 3D fin structure and the lower thermal conductivity of the SiO2 dominated substrate can cause local heat to get trapped.

With such tough challenges and extremely tight window of accuracy, it’s critical to ensure power integrity across the chip, package and board. And an accurate EM analysis at all levels is a must. There are some key critical enhancements added into ANSYS tools to provide the kind of accuracy and versatility needed for the EM, power integrity and reliability solution at 10nm.

To support multi-patterning technology, ANSYS solution provides color-aware resistance extraction and EM analysis capability. And there is a complete system-to-block level EM analysis flow with color-aware metal-fill capability that delivers higher yield and performance along with accurate EM analysis.

To address the increasing difference in the current between signal and power rails, ANSYS solution provides various approaches to apply appropriate EM rating factors for signal and power analysis. At 10nm, there can be measurement issue between the drawn trapezoidal shape and the physical implementation of a wire in silicon. ANSYS provides a comprehensive wire width adjustment solution to compensate for the difference that leads to more accurate results in the EM analysis.

ANSYS solution provides thermal-aware EM methodology. Above diagram shows the Thermal-aware EM Flow at TSMC for the 16nm FF+ process node that uses RedHawk, Totem and Sentinel-TI. RedHawk/Totem along with Sentinel-TI uses foundry data to accurately compute the self-heat temperature on an IP or SoC. The temperature can be analyzed at instance or metal layer basis. A Chip Thermal Model (CTM) is generated for back-annotation into RedHawk or Totem. This methodology helps avoiding over-heating of the device, thus increasing its lifetime and reliability.

With increasing complexity and sizes of SoCs at lower nodes, challenge of managing capacity, performance, and parasitic effects also increases. RedHawk/Totem uses a novel Distributed Machine Processing (DMP) capability that can handle large power delivery network (PDN) and perform flat simulation with high performance and small memory footprint. RedHawk-CPA provides chip-package co-simulation and co-analysis within a unified environment that ensures integrity of power delivery on the complete chip and takes into account the impact of package parasitic, thus avoiding undesired hotspots.

The overall comprehensive solution provided by ANSYS delivers highly accurate results as needed at 10nm FinFET node and also reduces design turnaround time through its innovative methodology, algorithms, and multi-physics simulations. The Power Integrity and EM solutions are ready for 10nm FinFET based early design start. On earlier technologies, ANSYS solution for SoC/IP power integrity, noise, and reliability sign-off has been proven on thousands of successful silicon wins.