By Mark Gardner, Vice President and General Manager of the Packaging and Test Business Group, Intel Foundry
Rapid growth in compute requirements for system on chips (SoCs), artificial intelligence (AI) accelerators, and networking devices is pushing traditional semiconductor packaging to its limits. To move beyond the restrictions of single-reticle die sizes, the industry has adopted package architectures that enable combining multi-reticle die complex sizes, including high-bandwidth memory (HBM), in a single package. These multiple reticle systems allow for greater compute density and more complex integration than monolithic chips can provide. This evolution requires innovative packaging architectures to support expanded area, higher interconnect density, and enhanced power and thermal management to meet the needs of next-generation devices.
Intel Foundry’s Advanced Packaging Innovations Lead the Industry in Scaling Past Reticle Limits
By Mark Gardner, Vice President and General Manager of the Packaging and Test Business Group, Intel Foundry Rapid growth in compute requirements for system on chips (SoCs), artificial intelligence (AI) accelerators, and networking devices is pushing traditional semiconductor packaging to its...
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