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From Medical and Wearables to Big Data, in 日本語/한국어/中文

From Medical and Wearables to Big Data, in 日本語/한국어/中文
by Paul McLellan on 04-10-2015 at 7:00 am

 Whether it’s a tiny always-on medical device or a secure cloud network processing Big Data, the Internet of Things (IoT) is bringing new challenges to IC design. Almost by definition an IoT device contains a microcontroller of some sort along with some way of communicating. Unlike our smartphones where we are reasonably happy if they last all day before requiring a charge, IoT systems, and thus the chips in them, have to last much longer. Current wearables such as Fitbit will last a week but some IoT devices are expected to last much longer, perhaps their whole lifetime, without a charge. Or even to scavenge power from the environment. Under those constraints, every tiny bit of power is important. To make things worse, many of these devices are likely to be “always on” meaning that at least a small part of the design must be permanently powered up to notice when something interesting happens. Both active power and static power are critical for maintaining long battery life. Therefore optimizing for very low voltage as well as very low leakage is important. These devices typically operate significantly below 100MHz.


One of the big challenges in these types of conditions is having memory that works reliably. Most available memory IP is not optimized for these criteria. Most semiconductor foundries prefer to develop and manage the SRAM bitcells. Because SRAM cells are limited by stability (or static noise margin) and write ability (or write margin) the lowest operating voltage (VDDMIN) is carefully specified. The random threshold variations in subnanometer technologies have resulted in serious yield issues for realizing low VDD READ/WRITE operations with a typical 6T SRAM cell. The use of different cell topologies may improve the SRAM stability at low operating voltages.

eSilicon has developed statistical simulation techniques to determine statistical failure probability distributions for low-voltage failure modes for various bitcell topologies. Bitcell read current, read-disturb margin, write margin, minimum data-retention voltage (MDRV), and leakage current are all thoroughly analyzed. These techniques enable quantification of actual failure rates as a function of critical process parameters, temperature, voltage, and design parameters. Effective design optimization for optimum VDDMIN, power, performance, and yield is enabled by these efficient simulation techniques. The result is a series of optimized SRAM architectures that operate below 100MHz, below 0.7V, and at one-fourth the leakage power of other available SRAM compilers at 65nm, 55nm, 40nm and 28nm technologies.

Associative lookup structures lie at the heart of many computing problems and content-addressable-memories (CAMs) provide fast constant time lookups over a large array of data (content keys) using dedicated parallel match circuitry. The two most common search-intensive tasks that use CAMs are packet forwarding and packet classification in Internet routers. For a lot of these applications, ternary CAM (TCAM) is an even more powerful primitive, able to simultaneously search through a large number of subspaces of a higher dimensional space in one shot. eSilicon’s 14/16nm TCAM compiler offers 1 gigasearch/s under worst-case conditions with low- power search features.


eSilicon have created a white paper From Medical and Wearables to Big Data: Differentiated IP for the IoT Spectrum available here.

eSilicon also created a webinar recently on this topic, focusing on ultra-low-power and ultra-low-voltage memory solutions. This webinar was, by far, the most popular eSilicon have done. Interest came from all over the globe. When the replay went up, interest again came from all over the globe (see the map below).

eSilicon decided to do something that they have never done before, they presented the webinar 3 more times in Japanese, Korean and Chinese. So you can watch:

  • In English with Lisa Minwell presenting, Senior Director of IP Marketing eSilicon
  • In Japanese 日本語 with Zenda Nguyen, Program Manager, IP Business Unit, eSilicon Vietnam
  • In Korean 한국어 with Taeho Kim, Country Manager & GM, eSilicon Korea
  • In Chinese 中文 with Kar Yee Tang, IP Product Marketing Manager, eSilicon


All four videos are available for replay here.


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