An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes

An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes
by Scotten Jones on 02-28-2017 at 12:00 pm

At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.… Read More


SEMICON West – Harry Levinson and Mike Lercel Interview

SEMICON West – Harry Levinson and Mike Lercel Interview
by Scotten Jones on 08-02-2016 at 12:00 pm

Image RemovedOn Tuesday morning at SEMICON I had the opportunity to sit down with Harry Levinson, Sr. Director of Technology Research and Sr. Fellow at Global Foundries and Michael Lercel, Director of Strategic Marketing at ASML to discuss the state of lithography.

I opened the discussion with a question about how we are going … Read More


Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?

Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
by Eric Esteve on 05-05-2016 at 7:00 am

More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More


ANSYS Enters the League of 10nm Designs with TSMC

ANSYS Enters the League of 10nm Designs with TSMC
by Pawan Fangaria on 04-09-2015 at 7:00 pm

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award.… Read More


Translating Intel

Translating Intel
by Scotten Jones on 01-28-2015 at 10:00 pm

Some of Intel’s technology posts make some pretty specific statements and I have seen a number of posts where people seem to have misinterpreted what Intel was actually saying.

Multi Patterning
I have seen a lot of confusion on this one with some people saying Intel didn’t use multi patterning at 22nm and others saying Intel used … Read More


FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


450mm Delayed and Other SPIE News

450mm Delayed and Other SPIE News
by Scotten Jones on 03-04-2014 at 11:00 pm

Image RemovedLast week I attended the SPIE Advanced Technology Conference. There were a lot of interesting papers and as is always the case at these conferences, there was a lot of interesting things to learn from talking to other attendees on the conference floor.

The first interesting information from the conference floor was… Read More