Ceva MotionEngine Hear Banner SemiWiki sizes 800x100 201124
WP_Term Object
(
    [term_id] => 158
    [name] => Foundries
    [slug] => semiconductor-manufacturers
    [term_group] => 0
    [term_taxonomy_id] => 158
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1079
    [filter] => raw
    [cat_ID] => 158
    [category_count] => 1079
    [category_description] => 
    [cat_name] => Foundries
    [category_nicename] => semiconductor-manufacturers
    [category_parent] => 0
)

Translating Intel

Translating Intel
by Scotten Jones on 01-28-2015 at 10:00 pm

Some of Intel’s technology posts make some pretty specific statements and I have seen a number of posts where people seem to have misinterpreted what Intel was actually saying.

Multi Patterning
I have seen a lot of confusion on this one with some people saying Intel didn’t use multi patterning at 22nm and others saying Intel used multi patterning at 14nm for the first time. Lets start with where I think the root of this problem began.


At the Intel Developers Forum in 2012 Mark Bohr gave a presentation and on page 37 Bohr discusses the 80nm minimum pitch metal being done with single patterning. I believe Mark Bohr even made some comments in one of his presentations that 80nm was picked because it is the smallest pitch than can be produced without resorting to multi patterning.

I believe this comment is what has led several people to conclude that Intel didn’t use multi pattering at 22nm when in fact what Mark Bohr was saying was they didn’t use multi patterning in the Back End Of Line (BEOL).

In the Front End Of Line (FEOL) Intel did use multi pattering. At Semicon in 2012 Mistry disclosed that Intel uses SDAP for the STI/Fin layer at 22nm. The fin pitch for Intel’s 22nm process is 60nm, much smaller than the 80nm pitch that can be done with a single immersion lithography exposure.

Interestingly this is not even the first Intel process to use multi patterning. As the industry moved to smaller and smaller pitches the exposure techniques in use changed to produce the smaller pitches required. At the 350nm node most companies introduced Krypton Fluoride (KrF) exposure and used KrF for critical layers at 350nm, 250nm, 180nm and 130nm nodes. At the 90nm node most companies introduced argon fluoride (ArF) exposure and used it for critical masks at the 90nm and 65nm nodes. At the 45/40nm node most companies introduced argon fluoride immersion lithography (ArFi), however Intel decided to stay with ArF for their 45nm node. The way they accomplished this was to use double pattering at the gate layer (per Holt in an interview with SST in 2007).

Intel introduced ArFi at the 32nm node although some SEM shots I have seen suggest Intel may have continued to use double pattering at gate for 32nm (presumably ArFi) and also at 22nm, but I am not certain of this. I do know they double patterned gate at 45nm and the STI/Fin layers at 22nm.

Of course at 14nm is when we really see multi patterning used extensively by Intel. Based on the information I have seen I believe the STI/Fin layer is done with SADP with 2 cut masks, gate, contact, M0, and the M1 through M5 layers with associated vias are all done with SADP with single cut masks.

The following table summarizes multi pattering at Intel by node.

[TABLE] align=”center” border=”1″
|-
| style=”width: 127px” |
| style=”width: 83px; text-align: center” | 45nm
| style=”width: 84px; text-align: center” | 32nm
| style=”width: 84px; text-align: center” | 22nm
| style=”width: 90px; text-align: center” | 14nm
|-
| style=”width: 127px” | Multi pattern layers
| style=”width: 83px; text-align: center” | 1
| style=”width: 84px; text-align: center” | 1?
| style=”width: 84px; text-align: center” | 1-2
| style=”width: 90px; text-align: center” | 14
|-
| style=”width: 127px” | Additional/cut masks
| style=”width: 83px; text-align: center” | 1
| style=”width: 84px; text-align: center” | 1?
| style=”width: 84px; text-align: center” | 1-2
| style=”width: 90px; text-align: center” | 15
|-

Air Gaps
During their IEDM presentation on 14nm this year Intel presented delay data for air gaps on metal layers M4 and M6. This led some people to conclude Intel uses air gaps on M4 and M6. My understanding is that analysis of actual parts in the field shows air gaps on M5 and M7. This suggests to me that the test chip where the data was measured had air gaps on M4 and M6 and they presented that data, but production is M5 and M7.


Comments

0 Replies to “Translating Intel”

You must register or log in to view/post comments.