WP_Term Object
    [term_id] => 77
    [name] => Sonics
    [slug] => sonics
    [term_group] => 0
    [term_taxonomy_id] => 77
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 49
    [filter] => raw
    [cat_ID] => 77
    [category_count] => 49
    [category_description] => 
    [cat_name] => Sonics
    [category_nicename] => sonics
    [category_parent] => 14433

NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers

NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
by Paul McLellan on 01-29-2015 at 7:00 am

At the end of last year, I moderated a Sonics webinar to introduce the concept of a network-on-chip or NoC. It was called NoC 101 and the replay is still available here.

Well it is a new year and time for chapter 2. I will be moderating a webinar next Wednesday February 4th at 10am pacific time. Once again the webinar itself will be delivered by Drew Wingard who is the CTO of Sonics. It is entitled NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers.

The performance and power requirements are very different for IoT devices such as wearables, and big server SoC. But it turns out that the same underlying technology, the NoC, can be used in both cases to integrate the large numbers of IP blocks that might be involved, handle the power domains and often the powering up and down of individual blocks of IP.

Modern mobile devices are increasingly pushed to provide greater functionality at lower power. Improved architectures provide the most effective approach to minimizing power by dividing the SoC into a multitude of power and clock domains, ensuring that each domain operates at the lowest power level to satisfy the application requirements. The on-chip network increasingly plays a critical role in both supporting larger numbers of domains and enabling rapid, safe power-state transitions. The arrival of ultra low power devices (and ultra low power processes) is only going to make this more challenging.

Furthermore SoCs utilizing multicore processors often require very high bandwidth communication capabilities between processors, between processors and accelerators, and between these components and a main memory store. The design of these complex devices presents many challenges for the SoC designer. One of those challenges is power management. Power consumption is important for all categories of Multicore SoCs, from battery operated devices where power savings can lead to smaller batteries and/or longer battery life, to line powered devices where power savings are important for cooling reasons as well as packaging and component costs. Even in high performance data centers, electricity and cooling costs can significantly exceed equipment costs.

The Network-on-Chip (NoC) providing on-chip communication plays an important role in the power management strategy of a multicore SoC. This webinar will address many of the techniques used to manage power consumption. These include fine-grain and course-grain clock gating techniques as well as voltage scaling and power switching with auto-wakeup capabilities. Building these techniques into the NoC simplifies the task of implementing an efficient power management strategy at the SoC level.

You can register for the webinar here.

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