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Because that is where the SoC power is

Because that is where the SoC power is
by Don Dingee on 06-15-2016 at 4:00 pm

Still thinking of Sonics as just a network-on-chip company? They are pivoting to become an SoC realization company, and in their seminar at #53DAC in Austin we saw an entirely new plan focused on heisting an extremely valuable commodity everyone else is missing.

CEO Grant Pierce opened the remarks with some love for Miles Davis – “it’s the notes you don’t play” that matter – to set the tone for the Energy Processing Unit that leverages idle moments. It was another comment Pierce made in introducing CTO Drew Wingard that stuck with me, a reference to the Willie Sutton response to the question of why he robbed banks. The obvious answer, which Sutton later disclaimed:

Because that’s where the money is.

I’ve never considered Drew as a bank robber type, but casting him as a scientist robbing SoCs for power savings fits perfectly. The premise of an EPU is power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the SoC – leaving the CPU to do real work.


When pointing out the “haves” and the “have nots” in power management, those companies with big design teams and power management specialists and lots of IP working on huge application processors versus everyone else with smaller teams and fewer tools, Wingard paused for audience input. Paraphrased to protect the innocent, it’s a pain point, but those “haves” usually feature a “god” type that oversees system-level issues like power management, and IP targeting that may be democratizing their job.

That’s like assigning a bank guard to oversee Bitcoin – a great way to miss almost all the action.

We introduced the concepts of the EPU in our prior post (link at end). This seminar ended with a short demonstration by Luc Ton of an Eclipse-based environment to create and management the ICE-Grain controllers in a state machine format leveraging constructs from UPF – it’s easy. Instead of the how, I want to concentrate on why looking at the opportunity Wingard explored in his case studies.

Video decoding is everywhere, and it sucks power from a mobile device. To get a sense of the possibilities, Wingard picked the Google G2 VP9 Decoder IP. It’s free, it handles 4K UHD decoding, and it takes about 3.9M gates in TSMC 28HPM. (One important point is designers must still pay attention to process and inherent leakage power first.) In conventional thinking, designers minimized the display power and “optimized” the video decoder, but saving power between frames during playback was impractical.


As it turns out, a UHD decoder at 500 MHz is idle a lot – it’s way overdesigned. True, while playing 2160p60 video the decoder is 97% active, but most of the content on the web is 480i60 or 720p30, and the decoder is only 2% and 5.4% active respectively at that clock rate. Of course, you could reduce the clock rate, dropping dynamic power but increasing active leakage power. By combining pacing with source clock gating and power gating between frames using an EPU approach, active leakage power is managed and a 94% energy reduction at 480i60 resolution is achieved.

Saving power between lines is impossible under software control, but in an ICE-Grain context with fast hardware one can get in between lines even at 2160p60. With a 3 ICE-Grain distributed state machine handling 4.7 MSPS (million states per second), Sonics can take out 41% of the energy in the CPIPE block while decoding 2160p60. 10 ICE-Grains applied over the rest of the pipeline deliver 11.7 MSPS and an overall power savings of 36%. It’s mind boggling to think there is that much money, er, power just laying around for the taking – and that’s just one IP block.


This blows the door off the myth – actually, it’s a reality in software-managed approaches – that thrashing defeats power savings. By creating fast, deterministic, distributed hardware that can maneuver inside idle moments, Sonics is redefining the opportunity for architectural power management with this strategy. We should note that ICE-Grains are not using the Sonics NoC, but a simplified 2 or 3 wire interface to support some IP block power acknowledge signals, and an ICE-Grain adds only 0.004% leakage. Chips with the ICE-G1 EPU are in tape out now, and Sonics is exploring collaboration with other EDA tool vendors, particularly the UPF proponents.

Our prior introduction to this topic:
Sonics opens new strategy for SoC energy processing