Changes Coming at the Top in Semiconductor Equipment Ranking

Changes Coming at the Top in Semiconductor Equipment Ranking
by Robert Castellano on 12-10-2018 at 12:00 pm
Categories: Information Network, Semiconductor Services
3 Comments

Semiconductor equipment vendor ranking, which didn’t change much between 2016 and 2017, is undergoing a makeover, as Lam Research, ASML, and Tokyo Electron (TEL) are switching places and top-ranked Applied Materials is getting closer to losing its number one ranking.

Since the 1990s, Applied Materials has been the market leader… Read More

January 28, 2015

Translating Intel

Translating Intel
by Scotten Jones on 01-28-2015 at 10:00 pm
Categories: Foundries

Some of Intel’s technology posts make some pretty specific statements and I have seen a number of posts where people seem to have misinterpreted what Intel was actually saying.

Multi Patterning
I have seen a lot of confusion on this one with some people saying Intel didn’t use multi patterning at 22nm and others saying Intel used … Read More

October 5, 2014June 14, 2019

10nm, the View from IBM

10nm, the View from IBM
by Paul McLellan on 10-05-2014 at 7:01 am
Categories: Cadence, EDA

On the Cadence booth at DAC, Lars Liebmann of IBM presented on the challenges of 10nm. As he put it, how the lithography folks are keeping things very interesting for the EDA tool development engineers. Although 14nm/16nm hasn’t yet ramped into HVM, the advanced work for tools and IP has all moved to 10nm. Although Lars gave… Read More

March 19, 2014

Triple Patterning

Triple Patterning
by Paul McLellan on 03-19-2014 at 1:00 pm
Categories: EDA, Foundries

As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.

In the litho world they call double patterning… Read More

November 20, 2013June 14, 2019

The Rosetta Stone of Lithography

The Rosetta Stone of Lithography
by Paul McLellan on 11-20-2013 at 3:14 pm
Categories: EDA

At major EDA events, CEDA (the IEEE council on EDA, I guess you already know what that bit stands for) hosts a lunch and presentation for attendees and others. This week was ICCAD and the speaker was Lars Liebmann of IBM on The Escalating Design Impact of Resolution-Challenged Lithography. Lars decided to give us a whirlwind tour … Read More

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Upcoming Events

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GPU-Powered SPICE: The Way Forward for Analog Simulation Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

Avoiding Charged Device Model Failure Fabless: The Transformation of the Semiconductor Industry

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Tag: sadp

Changes Coming at the Top in Semiconductor Equipment Ranking

Translating Intel

10nm, the View from IBM

Triple Patterning

The Rosetta Stone of Lithography

Upcoming Events

CDNLive Japan 2019

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