Last week I attended the SPIE Advanced Technology Conference. There were a lot of interesting papers and as is always the case at these conferences, there was a lot of interesting things to learn from talking to other attendees on the conference floor.
The first interesting information from the conference floor was that 450mm is being pushed out. What I heard is that with low fab utilization and the empty fab 42 shell, Intel has pulled all of their resources off of 450mm. Intel was one of the key players pushing 450mm and the comments I heard were 450mm won’t be this decade with 2023 as the new introduction date for high volume manufacturing. Some equipment companies appear to be putting 450mm equipment development on hold.
I think it is fair to say the conference was generally negative on EUV:
TSMC presented a paper where they really called out ASML. TSMC showed a chart of roughly a decade of ASML source power roadmaps where each roadmap shows a huge increase in the source power in the near future, and yet the reality is that source power has come up very little. TSMC has also seen low uptime on the sources on the systems they have in house (~70%). TSMC has an NXE3100 and recently received a NXE3300. On the NXE3300 system they had a laser misalignment in the source and the CO2 laser that vaporizes the tin to make EUV light damaged other components requiring extensive repairs. The key issues with EUV at present are source power and reliability and mask defects, the lack of progress on source power is a huge issue.
SEMATECH presented a paper on what it will take to get to high numerical apertures for EUV systems. The current NXE3300 is a 0.33 NA system that can produce the 10nm Logic node with a single exposure. For the 7nm logic node further improvements should be able to maintain single exposure but at 5nm a significant improvement in NA is likely required. In the SEMATECH talks they reported that to get NA above 0.4 more mirrors are required in the optical path. EUV mirrors have non negligible absorbance of EUV light reducing throughput. Also the system may have to go to higher magnification with either smaller field sizes or the mask size will have to grow from the current 6” to 9” or 12”. Increasing mask size is a huge undertaking requiring retooling throughput the mask supply change.
There were many other papers on EUV with Shot noise and pellicles being other interesting topics but I thought these two really made clear the challenges of getting EUV into production and then scaling it further. EUV is already late enough that it will likely miss the 10nm logic node and so 7nm and 5nm performance really becomes a key.
Interestingly there seemed to be a lot of optimism that we can achieve the 10nm, 7nm and possibly 5nm nodes by combining multi patterning with other techniques. There were a lot of papers on novel multi patterning schemes and shrink technologies. New immersion systems discussed by ASML and Nikon are promising 250 wafers per hour reducing exposure costs. There is a lot of work being done on simplification of the schemes. There is also help from the design and process technology side with increasing use of gridded designs and 3D memory. In 2013 Samsung introduced a 3D NAND technology that achieved bits/cm2 density similar to 1x NAND using a roughly 50nm lithography technology. The ability to scale memory in third dimension is a kind of equivalent scaling technique that can continue “scaling” with less pressure on exposure systems.
The key on multi patterning with other techniques will be cost. Quadruple and even Octuple pattering with up to 5 and 9 cut masks respectively looks like very expensive solutions. My company is the world leader in semiconductor cost modeling and we are currently doing a lot of work evaluating the economics of the various options. As we get though our work on cost projections I will post some observations.
There were also a lot of papers on Self Directed Assembly, Nano Imprint, E beam and other alternative but generally these techniques strike me as a lot further away from volume manufacturing.
One last personal observation, this was my first time at Advanced Lithography. I was very surprised to learn you don’t get the proceedings until six week or more after the conference. At other conferences I attend you get the proceedings on a memory stick when you arrive. I find being able to read the papers before seeing them presented and then go back and check them again after seeing the paper key to understanding the content. At paper after paper I was furiously taking notes as the information flew by and only captured a fraction of it. If anyone from SPIE reads SemiWiki, this is in my opinion a huge issue with your conference.
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