The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadenceadded new timing-closure automation to their Allegroproduct family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant Shah of Cadence by phone to learn more about timing closure of PCB designs.
PCB routing where each color shows different timing margins
What’s Wrong with Manual Timing Closure?
Let’s say that your new system is using DDR3 memory chips and that you need to reach timing closure on the PCB routing between the memory controller and DRAM.
You start to sketch out the timing diagrams for each group of signals.
Timing relationships for DDR3
When you start to do the PCB routing there’s an iterative process of fixing one byte lane, fixing another, then going back to fix the first byte lane. All of the signals have to meet their timing specifications in order for the entire group to change colors and turn green, for acceptable timing.
Timing closure challenges
There is clearly room for improvement in this iterative PCB routing and analysis steps. IC designers have long enjoyed using built-in timing analysis, concurrent with place and route to shorten timing closure, so it’s about time that a similar approach was brought into the PCB routing experience.
Allegro Approach for Concurrent Timing and Routing
Engineers at Cadence have embedded a concurrent timing engine during PCB routing, and this timing engine will analyze all of the interdependencies and then come up with its own delay and phase targets. This automated approach helps PCB designers by providing real time, visual feedback on design canvas.
Let’s take a quick look at an example where the TimingVision tool is using an Auto-interactive Delay Tuning (AiDT). First you select the complete interface, and then select a byte lane to tune:
After using AiDT the PCB results show that green is good, red is short and yellow is long. All of the nets in our selected byte lane met timing, automatically. This process takes only minutes for an engineer to tune the complete interface.
What about routing differential pairs? Good news, there’s a technique called Auto-interactive Phase Tuning (AiPT) which will meet your differential pair phase requirements, using both static and dynamic phase compensation.
There are two modes that you can use TimingVision:
- DRC Timing Mode – used at the end of a project. When all of the signals turn green then the specifications are met
- Smart Timing Mode – used early in a project. a new target signal is identified in your match group, then new min/max goals are developed based upon all the signals in the interface, finally signals go green as each one meets their independent min/max goal
For differential phase, you also have two modes of using TimingVision: DRC and Smart Phase.
For signal integrity and power integrity it is recommended to also run the Sigrity Power-Aware SI analysis after TimingVision.
Who Is Already Using TimingVision?
One customer willing to share some real results is PEGATRON, a Taiwanese ODM. Using AiDT in TimingVision they were able to tune a Server Board in just 5 hours, compared to 15 hours with manual methods, for a time savings of 67%. Similar results were found when PEGATRON used AiDT on a Tablet Board and tuned in just 3.89 hours, while manual methods required 12 hours.
If you are using Allegro today for PCB design and spending way too much time trying to manually reach timing closure, then give TimingVision a try, it is included in the high-speed option of Allegro. Early results from customers of TimingVision show promising savings in timing closure.