This is the first time in 28 years of my visits to DAC that I have seen so many different technologies arrive at DAC in the same year. Earlier we would have one or possibly two innovative breakthroughs in semiconductors and embedded systems that emerged at DAC. This year I expect six or may be seven to arrive, and I am not including the… Read More
– KLAC reported an OK QTR & flat guide-waiting for 2025 recovery?
– China exposure remains both risk & savior & big in backlog
– Wafer inspect strong- Patterning on long slide- PCB biz for sale
– Some bright spots but memory still weak- Foundry/Logic OK
– Lam reported as expected and guided flat- No recovery yet
– Some mix shifts but China still 40% (8X US at 5%)-NVM still low
– HBM is promising but Lam needs a broad memory recovery
– Lam has not seen order surge ASML saw- Likely lagging by 3-4 QTRs
As compared… Read More
TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched. Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More
At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5… Read More
Throughout its history, the ASIC industry has had its ups and downs. With feast and famine cycles, the ASIC business model is not for the faint of heart. Some companies tread boldly while others dread the cycles and stay away from this business model. Those who are consistently successful have to overcome many challenges thrown … Read More
In a discussion with Tom Fitzpatrick of Siemens EDA he recalled that their Verification Horizons newsletter started 17 years ago, back when they were Mentor. We’ve known about the Siemens acquisition for a while. The deal closed in March 2017, but it wasn’t until January 1, 2021 that the legal entity merger was complete. Which makes… Read More
80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
Synopsys announced on October 24 new DesignWare[SUP]®[/SUP] Memory Interface IP solutions supporting the next-generation DDR5 and LPDDR5 SDRAMs. The DDR5 and LPDDR5 IP significantly increase memory interface bandwidth compared to DDR4 and LPDDR4/4X SDRAM interfaces, while reducing area and improving power efficiency.… Read More
Will we see DDR5 memory (device) and memory controller (IP) in the near future? According with Cadence who has released the first test chip in the industry integrating DDR5 memory controller IP, fabricated in TSMC’s 7nm process and achieving a 4400 megatransfers per second (MT/sec) data rate, the answer is clearly YES !
Let’s come… Read More
