At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5… Read More
Throughout its history, the ASIC industry has had its ups and downs. With feast and famine cycles, the ASIC business model is not for the faint of heart. Some companies tread boldly while others dread the cycles and stay away from this business model. Those who are consistently successful have to overcome many challenges thrown … Read More
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?
• Do you need to size the AI accelerator for existing and future AI requirements?
• Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks?
This webinar focuses on design teams… Read More
In a discussion with Tom Fitzpatrick of Siemens EDA he recalled that their Verification Horizons newsletter started 17 years ago, back when they were Mentor. We’ve known about the Siemens acquisition for a while. The deal closed in March 2017, but it wasn’t until January 1, 2021 that the legal entity merger was complete. Which makes… Read More
80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
Samsung is a complicated company with a VERY long history. We attempted to capture the Samsung Experience in chapter 8 of our book “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices”. If you are a registered SemiWiki member you can download a free PDF copy in our Books section.
Here is the chapter 8 … Read More
Synopsys announced on October 24 new DesignWare[SUP]®[/SUP] Memory Interface IP solutions supporting the next-generation DDR5 and LPDDR5 SDRAMs. The DDR5 and LPDDR5 IP significantly increase memory interface bandwidth compared to DDR4 and LPDDR4/4X SDRAM interfaces, while reducing area and improving power efficiency.… Read More
Will we see DDR5 memory (device) and memory controller (IP) in the near future? According with Cadence who has released the first test chip in the industry integrating DDR5 memory controller IP, fabricated in TSMC’s 7nm process and achieving a 4400 megatransfers per second (MT/sec) data rate, the answer is clearly YES !
Let’s come… Read More
Machine learning is transforming how information processing works and what it can accomplish. The push to design hardware and networks to support machine learning applications is affecting every aspect of the semiconductor industry. In a video recently published by Synopsys, Navraj Nandra, Sr. Director of Marketing, takes… Read More
According with IPnest, the Interface IP market, including USB, PCI Express, (LP)DDRn, HDMI, MIPI and Ethernet IP segments, has reached $532 million in 2016, growing from $472 million in 2015. This is an impressive 13% Year-over-Year growth rate, and 12% CAGR since 2012!
Who integrate functions to interface a chip with others … Read More
