– KLAC reported an OK QTR & flat guide-waiting for 2025 recovery?
– China exposure remains both risk & savior & big in backlog
– Wafer inspect strong- Patterning on long slide- PCB biz for sale
– Some bright spots but memory still weak- Foundry/Logic OK
– Lam reported as expected and guided flat- No recovery yet
– Some mix shifts but China still 40% (8X US at 5%)-NVM still low
– HBM is promising but Lam needs a broad memory recovery
– Lam has not seen order surge ASML saw- Likely lagging by 3-4 QTRs
As compared… Read More
November 28, 2023 | 1:00 PM EST
Memory interface speeds keep increasing to meet performance demand. For instance, DDR5 is 275% faster than DDR4, reaching 8800 MT/s or more. Higher speeds also complicate memory design and validation. To achieve the next memory standard, designers need a connected workflow that streamlines… Read More
TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched. Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More
At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5… Read More
Throughout its history, the ASIC industry has had its ups and downs. With feast and famine cycles, the ASIC business model is not for the faint of heart. Some companies tread boldly while others dread the cycles and stay away from this business model. Those who are consistently successful have to overcome many challenges thrown … Read More
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?
• Do you need to size the AI accelerator for existing and future AI requirements?
• Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks?
This webinar focuses on design teams… Read More
In a discussion with Tom Fitzpatrick of Siemens EDA he recalled that their Verification Horizons newsletter started 17 years ago, back when they were Mentor. We’ve known about the Siemens acquisition for a while. The deal closed in March 2017, but it wasn’t until January 1, 2021 that the legal entity merger was complete. Which makes… Read More
80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design. RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities. Can it really attain the utopian success that people are looking… Read More
Samsung is a complicated company with a VERY long history. We attempted to capture the Samsung Experience in chapter 8 of our book “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices”. If you are a registered SemiWiki member you can download a free PDF copy in our Books section.
Here is the chapter 8 … Read More
