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WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library

WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library
by Daniel Nenni on 07-26-2021 at 6:00 am

Aug5 TechTalk 2 hybrid processing80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design.  RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities.  Can it really attain the utopian success that people are looking for?  Is the huge investment worth the performance, cost, and power returns? All of these require experimentation that is not contingent on the exact implementation. Rather focus should be on what IP blocks should be in the solution, how should they be interconnected, what is the maximum workload, what is the instant power, and what are the most suitable applications.  Developing iterations of silicon and FPGAs can provide coverage in the 10’s of products.  The designer must be looking at 1000’s of use-cases.  This can only be achievement using system-level studies.  The major impediment to system architecture exploration and trade-offs is the lack of architecture models for high-end cores, interconnects, caches, and memories.


Hybrid Processing is a new concept that is emerging in the system modeling space.  These models have the simulation speed of a stochastic model with the accuracy of a cycle-level model.  These Hybrid Processing Models have altered the system analysis approach.  The old way of building individual models for each device generation is out.  The new way is to build a baseline of models with sufficient set of parameters that can emulate all possible configuration.  Another off shoot of Hybrid Processing approach is to merge and integrate performance, power and functional analysis.  The timing accuracy and simulation speed enables designers to work at the IP/core, System-on-chip (SoC), and large distributed systems.

Mirabilis Design has taken an interesting extension to Hybrid Processing.  The company has developed models for over 500 commercial vendor products using just 23 library components.  There are components to emulate a processor, GPU, interconnect, cache, DMA, memory, network, and buses.  Using these basic blocks, the company provides architecture models for complex vendor products such as the Out-of-Order RISC-V cores with the current Instruction Set, SiFive u74MP, ARM Aa65AE, ARM Neoverse, Arteris FlexNoC and DDR5.  To take advantage of these high-quality libraries, Mirabilis Design provides a methodology that connects the requirements database to the simulation reports, thus providing closed-loop optimization of the system specification for the target application.  To ensure maximum collaboration, a highly distributed Discrete-Event Simulation Platform with an executable documentation generation


Mirabilis Design is co-hosting a Webinar with SemiWiki on August 5 to introduce Hybrid Processing and how it can bring greater accuracy, wider architecture coverage and a large design space exploration to system design.  During the Webinar, practical applications in high-performance computing, AI/ML and automotive ECU will be highlighted, along with the trends in System-on-chip topologies.  Some of the studies discussed are cache stashing, number of floating point and load/store execution units, workload distribution, hardware-software partitioning, Tensor and AI/ML, cores per cluster, using Big-Little core combination, and power management algorithms.

Also Read:

Architecture Exploration with Miribalis Design

CEO Interview: Deepak Shankar of Mirabilis Design

Webinar: System Level Modeling and Analysis of Processors and SoC Designs

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