WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library

WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library
by Daniel Nenni on 07-26-2021 at 6:00 am

Aug5 TechTalk 2

80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design.  RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities.  Can it really attain the utopian success that people are looking… Read More


Automating Timing Closure Using Interconnect IP, Physical Information

Automating Timing Closure Using Interconnect IP, Physical Information
by Majeed Ahmad on 04-29-2015 at 1:00 pm

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More