Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely inefficient process mired with uncertainty, can effectively turn into “timing experimentation” if the factors that delay or prevent timing closure are not addressed in the early stages of the design flow.
Today’s new, larger and more complex SoC designs are developed in even shorter timeframes and increasingly demand higher productivity in each phase of the design cycle. Increasing on-chip interconnect design efficiency has historically been key to the recent reductions in SoC design times because the on-chip network touches every IP on the chip and must adapt as the SoC design changes.
The interconnect fabric is akin to an SoC’s skeleton and nervous system, holding the SoC together and managing its on-chip communications while living in the narrow confines of the floorplan “white space” lanes between IP blocks. Increasing the efficiency of interconnect design automatically increases overall SoC design efficiency. However, as chips have grown in size and the number of IP blocks increased, the interconnect IP has become the major source of long timing paths that must be stretched through congested areas of the SoC. Because of these long paths, the interconnect fabric has become a major source of timing closure issues that until now were only uncovered in the back-end SP&R phases of the chip design process.
Arteris has launched FlexNoC Physical interconnect IP to automate timing closure
Physically Aware Interconnect IP?
Trying to solve physical timing closure problems by improving the on-chip interconnect IP seems strange at first, but makes sense when the fact that most timing issues arise from within the interconnect IP is understood. Furthermore, using the interconnect IP as a foundation to implement front-end technology that eases back-end design issues makes sense when you consider that Arteris Inc. claims to have 52 active customers and nearly 200 SoC projects. Moreover, the interconnect IP supplier from Silicon Valley is adding eight to 10 new customers every year (Arteris added nine in 2014).
Interesting fact: Most of the world’s smartphones use the Arteris FlexNoC IP fabric, and these application processors and digital baseband modems are exactly the types of complex SoCs that take the longest to close timing.
Arteris’ NoC technology has been on the forefront in minimizing wire routing congestion and reducing silicon area, cost and power consumption of all kinds of chips. Now Arteris is taking on the next interconnect challenge in the SoC design flow: Timing closure. The interconnect IP firm is doing this by leveraging its network-on-chip architecture to accelerate physical design.
The Campbell, California–based supplier of interconnect IP claims that it has developed a way for chip design teams to cut months off development time by automating the timing closure process through the use of physically aware network-on-chip interconnect fabric IP.
Interconnect is skeleton and nervous system of SoCs
Normally, SoC designs change eight to 10 times during a normal chip design lifecycle due to market and technical factors, and the problem of SoC design iterations is likely to get worse at smaller nodes like 16nm, 14nm, and 10nm. The fact that physical design is getting in the way of SoC development makes it imperative for chip developers to visualize the SoC project and see what’s going on from a physical aspect.
Arteris announced the availability of FlexNoC Physical interconnect IP at the Linley Mobile Conference on April 22, 2015. Arteris’ FlexNoC Physical interconnect IP has automated the placement of pipeline stage IP on long paths that cause timing closure issues.
Arteris President and CEO K. Charles Janac says that the FlexNoC Physical interconnect IP can help the RTL implementation team to automatically add pipelines for timing closure, cutting months off complex SoC development cycles. He added that the new interconnect solution helps SoC architects to visualize the physical implications of their typologies early in the design cycle and address the physical layout and floorplan issues prior to completing the back-end design.
How FlexNoC Physical Works
Usually, SoC teams over-design their chips in the front-end stage to avoid timing problems in the back-end, creating excess timing slack and increasing die area and power consumption. So FlexNoC Physical IPintelligently estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve desired frequencies. Moreover, SoC designers can generate interconnect floorplan outlines and treat the interconnect as a separate IP to carry out physical synthesis place-and-route independently. That simplifies the job of the layout team.
The physically aware interconnect IP determines where pipeline stages must be used and adds pipelines automatically. It evaluates all timing arcs in the NoC interconnect because distance and logic depth dictate number of pipeline stages. The interconnect IP first predicts and then implements pipeline location while minimizing area and latency.
Time closure with physical synthesis
Additionally, Arteris has developed a more effective data exchange between front-end and back-end design tools and IP to accelerate physical design by feeding the physical design better data. That speeds up layout with physically-aware interconnect IP, which in turn, allows isolating the NoC physical instance to optimize timing and routing.
Design teams can now optimize the NoC physical instance independently of the rest of SoC. The FlexNoC Physical solution leverages the architectural knowledge of the SoC interconnect to accelerate timing closure as well as improve layout quality of results (QoR) by using less slack to meet timing.
Using FlexNoC Physical IP can Help Avoid Disaster
Timing closure can take months, and mistakes can cause subsequent delays in the market introduction. Arteris claims that accelerating timing closure through the use of NoC interconnect fabric enables SoC designers to cut months off their development time and gets them to market faster.
Take the case of an SoC maker that ended up designing an un-manufacturable chip. The company had a very firewalled relationship between its front-end design, architecture team and back-end layout team. The front-end team created a design that couldn’t be placed by the back-end while meeting timing and frequency requirements. The chipmaker had to redo the design, which was eventually canceled.
The bottom line was that the firm paid more than twice the normal R&D costs for a chip that was never made. Obviously, $200 million is a lot of money to pay for a timing closure failure.
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