Chiplets have simplified one area of design but opened pandora’s box on another front. The simulation complexity of each chiplet is lower but now the chiplet-to-chiplet interconnect has become complex. Folks are experimenting with different interconnect protocols, variations of UCIe, modifying UCIe settings, interface speeds, number of physical layers and so one. Now add legacy standards like AXI, new protocols like PICe6.0 and cache coherency to the mix.
All-in-all, this creates a completely new set of experiments. One for which the traditional emulation and RTL modelling will not work. You need first spend an effort on architecture trade-off, not just in selecting components. This will mean that you will have to conduct traffic analysis, application partitioning, system sizing and impact of different types of physical layer. Also, depending on the application the benchmark will be very different.
The UCIe specification is new and there are no clear benchmarks. Also, the UCIe specification only provides guidance on latency and power. Both are stringent requirements. This means that a Power-Performance-Area study is evitable. As you have protocol-protocol-protocol conversion such as PCIe 6.0 to UCIe to AXI, the modelling setup is complex.
One solution is to look at system-modeling using VisualSim from Mirabilis Design. They have recently launched a UCIe System-level IP model and will be demonstrating a number of use cases of the interconnect at the Chiplet Summit. To guide designers along, they have published a guide with lots of use cases, expected power-performance results and options for optimization. They have both a paper presentation and a booth at the Summit. I hope to see you there!
Also, here is the link for a paper that folks can get: Performance modeling of a heterogeneous computing system based on the UCIe Interconnect Architecture
Today’s complex chip designs at leading-edge nodes generally consist of multiple dies (or chiplets). The approach allows for dies from different manufacturers or processes, as well as reusable IP. Designers need a system level model to evaluate different implementations of such complex situations.
An example system consists of an I/O chiplet, low power core chiplet, high-performance core chiplet, audio-video chiplet, and analog chiplet, interconnected using the Universal Chiplet Interconnect Express (UCIe) standard.
Our team considered several scenarios and configurations including advanced and standard packages, varied traffic profiles and resources, and a retimer to extend the reach and evaluate events on timeout. Identifying the strengths and weaknesses of the UCIe interconnect for mission applications helped us obtain the optimal configuration for each subsystem to meet performance, power, and functional requirements.
About Mirabilis Design Inc.
Mirabilis Design is a Silicon Valley software company, providing software and training solutions to identify and eliminate risk in the product specification, accurately predicting the human and time resources required to develop the product, and improve communication between diverse engineering
VisualSim Architect combines Intellectual Property, system-level modeling, simulation, environment analysis and application templates to significantly improve model construction, simulation, analysis and RTL verification. The environment enables designers to rapidly converge to a design which meets a diverse set of interdependent time and power requirements. It is used very early in the design process in parallel with (and as an aid to) the written specification and before an implementation (for example, RTL, software code, or schematic) of the product.