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Webinar – Comparing ARM and RISC-V Cores

Webinar – Comparing ARM and RISC-V Cores
by Daniel Payne on 10-14-2021 at 10:00 am

Operating systems and Instruction Set Architectures (ISA) can have long lifespans, and I’ve been an engineering user of many ISAs since the 1970s. For mobile devices I’ve followed the rise to popularity of the ARM architecture, and then more recently the RISC-V ISA which has successfully made the leap from university project to commercialization with a widening ecosystem of support.  Naturally the question arises as to which ISA fits a specific workload for the best efficiency, like: MIPS, latency, and the number of instructions.

One company that has expertise in answering these questions is Mirabilis Design, and they’re hosting a webinar about how to model and measure the efficiency of three popular cores:

  • ARM Cortex A53
  • ARM Cortex A77
  • SiFive U74

Mirabilis Design will show their models of these processors, and how to configure each processor model with settings for:

  • Clock Speed
  • Caches: L1, L2, DSU
  • AXI Speed
  • DRAM Speed
  • Custom switches

The same C code will be used across each processor, and the specific C compilers will be used. Simulations with the compiled code are run in the VisualSim tool, then the results of the simulations are compared to show metrics, like:

  • # of Instructions
  • Latency
  • Maximum MIPS
  • Cache hit-ratio
  • Memory bandwidth
  • Power

You will find out which ISA has the smallest # of instructions, ARM or RISC-V, meaning the best compiler efficiency, along with latency and MIPS numbers. With the Mirabilis Design approach it only takes minutes to run a simulation on your own C code, then collect all of the efficiency numbers for an ISA that you have configured. This information helps a system architect to detect any bottlenecks, and then optimize the architecture for best performance.


System architects and SoC design teams trying to decide which ISA to go with on their next project should be interested in this webinar. You can see the replay HERE.

Compare Performance-power of Arm Cortex vs RISC-V for AI applications.

In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores.

Aside from the processor resources such as cache and memory, the system will contain custom switches, Ingress/Egress buffers, credit flow control, DMA AI accelerators, NoC and AMBA AXI buses.

The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth.

The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.

Key Takeaways:
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model

Speaker Bios:
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP.

Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors, and embedded computing.

About Mirabilis Design
Mirabilis Design, a Silicon Valley company, designs cutting edge software solutions that identify and eliminate risks in product performance. Its flagship product, VisualSim Architect is a system-level modeling, simulation, and analysis environment that relies on libraries and application templates to vastly improve model construction and time required for analysis. The seamless design framework facilitates designers to work on a design together, cohesively, to meet an intermeshed time and power requirements. It is typically used for maximum results, early in the design stage, parallel to the development of the product’s written specification. It precedes implementation stages – RTL, software code, or schematic – rendering greater design flexibility.

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