At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated deal involving stock, people, products and cash).
2013 was a good year for Calypto with record revenues, including Q4 being the best revenue quarter ever. They ended the year with lots of cash in the bank too, which is great for a startup. In a startup, as Gordon Bell used to say, “cash is more important than your mother.” 2014 is starting out well with lots of customer engagements in high-level synthesis. In the power area, the move to FinFETs makes dynamic power a bigger problem, and since everyone has already done the easy stuff, this drives PowerPro business. SLEC is a sort of complement to both products, basically checking that nothing screwed up. The company is over 100 people and they plan to grow headcount 15-20% in 2014.
I asked Sanjiv if they have access to the Oasys synthesis technology that Mentor acquired at the end of last year. He said they are discussing it. Mentor and Calypto are separate companies (although Mentor owns a controlling interest in Calypto I have heard) so nothing is automatic. But the attraction of using Calypto’s HLS along with Oasys’s very fast RTL synthesis offers the possibility of going straight from C to placed-gates. There is also some possible synergy in the power area. Since Sanjiv used to be on the board of Oasys and did some of their marketing he knows the technology well.
HLS (from Mentor) and PowerPro/SLEC (from the original Calypto) are roughly 50:50 in terms of business. PowerPro is growing the fastest since it is part of an established RTL methodology whereas HLS is a methodology change which always takes time. But all 3 product lines are growing. Sanjiv told me that they will have several announcements this year, mostly in the second half. The only hint I could get from him is that one is something to do with power.
This feels like the year that HLS is going to take off. I guess Cadence feel it too, having just acquired Forte. I happened to be in the press room earlier today and overheard part of a roundtable about HLS. Devadas Varma, now at Xilinx, and coincidentally the founder and initial CEO of Calypto (and who I worked with at Ambit) was one of the participants. He worked at AutoESL and they were acquired by Xilinx and that technology is now part of Xilinx’s Vivado suite (as is Oasys’s synthesis technology that Xilinx licensed). He pointed out that clock rates have peaked at about 3GHz. It is just not possible to go faster due to power. So to get more performance, more parallelism is required. The best tool for handling that is HLS since it can automatically parallelize as much as you want, unrolling loops, duplicating functional units and so on. That is driving use of HLS inside Xilinx.
Today, the sweet spot for HLS is video since it is very complicated, the standards change all the time, and people care more about throughput than the precise number of clock-cycles. Perfect for HLS to make tradeoffs and come up with excellent implementations. More and more of the blocks that differentiate an SoC are using HLS to get that differentiation since it is too hard without. As a result the RTL level designers are starting to adopt HLS. The results that HLS can produce have improved enormously in the last year or two, so if you looked at the technology a few years ago and decided it wasn’t quite ready yet then take another look.
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