John Lee: Market Trends, Raising the Bar on Signoff

John Lee: Market Trends, Raising the Bar on Signoff
by Bernard Murphy on 06-07-2018 at 7:00 am

I talked to John Lee (GM of the ANSYS Semiconductor BU) recently about his views on market trends and the ANSYS big-picture theme for DAC 2018. He set the stage by saying he really liked Wally’s view on trends (see my blog on Wally’s keynote at U2U). John said these confirm what he is seeing – a trend to specialization, some around… Read More


Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping

Webinar: Aiding ASIC Design Partitioning for multi-FPGA Prototyping
by Bernard Murphy on 09-07-2017 at 4:00 pm

The advantages of prototyping a hardware design on a FPGA platform are widely recognized, for software development, debug and regression in particular while the ultimate ASIC hardware is still in development. And if your design will fit into a single FPGA, this is not an especially challenging task (as long as you know your way … Read More


FPGA Design Gets Real

FPGA Design Gets Real
by Tom Simon on 02-08-2017 at 12:00 pm

FPGA’s have become an important part of system design. It’s a far cry from how FPGA’s started out – as glue logic between discrete logic devices in the early days of electronic design. Modern day FPGA’s are practically SOC’s in their own right. Frequently they come with embedded processor cores, sophisticated IO cells, DSP,… Read More


Solutions for Variation Analysis at 16nm and Beyond

Solutions for Variation Analysis at 16nm and Beyond
by Tom Simon on 09-22-2016 at 7:00 am

Variation is still the tough nut to crack for advanced process nodes. The familiar refrain of lower operating voltages and higher performance requirements make process variation an extremely important design consideration. As far back as the early 2000’s design teams have been looking for a better approach to model variation… Read More


How to Deal With Seven Design Closure Issues

How to Deal With Seven Design Closure Issues
by Tom Simon on 05-02-2016 at 12:00 pm

The challenge of tracking design progress is a shared problem for individual designers, team leaders, and project managers. At each level the ability to step back from just reviewing error log files and seeing the arc of the whole design as it moves forward is valuable. The difficulty of seeing the whole picture is exacerbated when… Read More


An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the… Read More


FinFET: The Miller’s Tale

FinFET: The Miller’s Tale
by Paul McLellan on 05-27-2015 at 7:00 am

In Chaucer’s Canterbury Tales, the second of the tales told by the pilgrims is The Miller’s Tale. Since this is a family blog, I’ll leave you to research the tale yourself. But FinFETs hide another Miller’s Tale, due to Miller capacitance, sometimes called the Miller effect. This is significant since in FinFET designs Miller capacitance… Read More


A Complete Timing Constraints Solution – Creation to Signoff

A Complete Timing Constraints Solution – Creation to Signoff
by Pawan Fangaria on 09-28-2014 at 10:00 pm

With the unprecedented increase in semiconductor design size and complexity design teams are required to accommodate multiple design constraints such as multiple power domains for low power design, multiple modes of operation, many clocks running, and third party IPs with different SDCs. As a result timing closure has become… Read More


FinFET & Multi-patterning Need Special P&R Handling

FinFET & Multi-patterning Need Special P&R Handling
by Pawan Fangaria on 04-28-2014 at 1:00 pm

I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More


Signoff Accurate Timing Analysis at Improved Run-time & Capacity

Signoff Accurate Timing Analysis at Improved Run-time & Capacity
by Pawan Fangaria on 04-18-2014 at 4:30 pm

The semiconductor design sizes, these days, can easily be of the order of several hundred millions of cells, adding into the complexity of verification. Amid ever growing design sizes, it’s a must that the timing verification is done accurately. Normally Static Timing Analysis (STA) is done to check whether all clocks and signals… Read More