In Chaucer’s Canterbury Tales, the second of the tales told by the pilgrims is The Miller’s Tale. Since this is a family blog, I’ll leave you to research the tale yourself. But FinFETs hide another Miller’s Tale, due to Miller capacitance, sometimes called the Miller effect. This is significant since in FinFET designs Miller capacitance can be the dominant capacitative effect, even more than the wire loads themselves. Since existing STA tools and library models miss or understate this effect, this can lead to overestimation of circuit performance leading to yield or clock frequency problems in the unforgiving silicon.
So what is Miller capacitance? It is an effect well known to analog designers but largely ignored by digital designers who can ignore many second order effects for process node after process node until…well…until they can’t, which in this case is when we move to FinFETs. The Miller effect is the increase in input capacitance of an inverting amplifier (such as an inverter or a nand-gate) due to the amplification of the capacitance between the input and output terminals. For example, the diagram on the right shows an inverter with amplification A[SUB]v[/SUB] and an impedance Z between the input and output. If the physical input capacitance is C then the effective capacitance at the input, due to the Miller effect, is not just C but is actually C * (1 + A[SUB]v[/SUB]).
The Miller capacitance becomes much larger with FinFETs than planar, simply because of their three-dimensional structures. The gate, which wraps around the channel, has a much larger exposed surface area, which in turn creates greater potential for capacitance. The diagram to the right shows all of the parasitic capacitance points created by the surfaces in a FinFET. Capacitance will be a function of either overlap or surface area, so the increase in both overlap and surface creates more potential Miller capacitance in the FinFET than in older planar transistors.
The Miller Capacitance has two major impacts on circuit timing, both of which must be accounted for by delay calculation during static timing
Pretty much the simplest possible circuit is two inverters connected back to back as on the right. The plot below shows what happens when the first inverter is driven with a rising signal (shown in red). The output from the first stage is shown in green and is clearly non-linear. The “bump” in the waveform is due to the Miller capacitance. This has two effects. First, the delay has changed and the Miller capacitance has slowed the signal. And second the output signal is distorted and is not a simple linear ramp.
The output from the second inverter, driven by the green signal as its input, is shown in blue. It is very non-linear. If we added a third (and more) inverter it would be even more distorted.
Most production sign-off flows today ignore the Miller effect, even in FinFET technologies. They simplify the receiver model to a basic pin capacitance, and waveforms are linearized rather than correctly propagated. The result is that delay is understated. This is most acute on nets with multiple receivers (fanout) where the Miller effect is largest.
There are two reasons that timing using the CCS (composite current source) receiver model is not accurate:
Properly accounting for the Miller Capacitance requires correctly modeling the impact of an active load at both the driver and the receiver, and propagating the real waveform that results through the rest of the path.
A CLKDA white paper on the Miller effect is here.