WP_Term Object
(
    [term_id] => 18
    [name] => Intel
    [slug] => intel
    [term_group] => 0
    [term_taxonomy_id] => 18
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 377
    [filter] => raw
    [cat_ID] => 18
    [category_count] => 377
    [category_description] => 
    [cat_name] => Intel
    [category_nicename] => intel
    [category_parent] => 158
)

Apples Versus Zebras

Apples Versus Zebras
by Scotten Jones on 01-06-2015 at 12:00 am

 I have seen a couple of posts comparing the density of the Apple A8 to the Intel Core M and concluding that the TSMC 20nm process is denser than the Intel 14nm process. In one of the threads one of the posters likened this to comparing apples to oranges, I agree except I think it is even worse than that, I think it is more like comparing apples to zebras and here is why:

Let’s start by talking about the elements one might see in a chip design on these advanced processes. First there are logic elements. Depending on the design goals, density, power, and speed the logic elements will vary in size. They will also vary in size versus SRAM cache and SRAM cache itself will vary in size depending on the goals even on the same process. For example, TSMC’s 45nm process has high density SRAM cache with a 0.202 um2 cell size and other SRAM cache (presumably high performance) with a cell size of 0.324 um2, a 1.6x difference on the same process! Intel’s 22nm SOC process offers HDC cache with a cell size of 0.092 um2, LVC with a 0.108 um2 cell size and HPC with a 0.130 um2 cell size, a 1.4x difference! And these are just a few quick examples from scanning published papers on processes. Analog circuit elements will also have a different density particularly when considering that elements such as resistors and capacitors aren’t even counted towards the circuit density.

I have analyzed seven different Intel MPU designs I have data on, all were produced on the same Intel 32nm process. The designs vary from just over 2 million transistors per mm2 to over 5 million transistors per mm2, a 2.5x difference in density on the same process for different MPU designs executed by the same company! To compare the Apple A8 design that has a completely different set of design goals to an Intel Core M on two different processes and conclude one process is more or less dense than the other is simply not a valid comparison. You would need two identical or close to identical designs on the two different processes to make a valid comparison and in this case that isn’t available. This is why at all the major technical conferences, all of the companies use design independent minimum pitches to compare processes.

Lately I have made several posts using the gate pitch x metal pitch metric to compare relative process density. This is a metric Intel has used in several recent presentations; IBM and the common platform alliance have also used it in their own technical papers. Even TSMC when disputing an Intel density advantage claim didn’t question the metric, they merely said Intel used old numbers for TSMC. The best and indeed only valid design independent comparisons of processes currently available are SRAM cell size and gate pitch x metal pitch which is why process experts use them.

I think it is fair to say that process experts generally agree that Intel has the densest 16nm/14nm logic process currently available, but so what? The more relevant question is whether Intel’s 14nm process is the best process and that depends on your design goals. Intel’s processes are first and foremost designed to produce Intel MPUs, and then the processes are adapted to make SOCs. TSMC processes are developed in close coordination with their customers and are specifically targeted at the SOC needs of those customers. I would bet money that if Apple knocked on Intel’s door and wanted to make the A9 on Intel’s 14nm process, Intel would be interested, in fact I would be surprised if Apple hadn’t at least evaluated that option. Apple makes the A8 on TSMC’s 20nm SOC process because they concluded that at the time they did the design that was their best option from a performance, price and delivery perspective for Apple’s design goals. I have no doubt the A9 sourcing decision will be made based on the same criteria.

Intel’s processes look different from TSMC’s processes because their design goals are different and TSMC’s processes look different than Intel’s process because TSMC’s customers have different design goals. TSMC is far and away the market leader in foundry and their process development is targeted at maintaining that lead. Intel is far and away the market leader in MPUs and their process development is targeted at maintaining that lead. One company makes apples and one company makes zebras, they both do it really well.

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