In the late 1990s and early 2000s, during the adolescent days of the system-on-chip (SoC) design movement, there was a lot talk about IP and design reuse, but it was seldom put into practice. A decade later, SoC turned into a juggernaut with a tripartite alliance of chipmakers, IP suppliers and semiconductor manufacturing fabs.
The internal and external IPs became a key building block in modern SoCs due to a number of semiconductor industry developments. For a start, the leading-edge SoCs continued their journey toward smaller nodes while striving to overcome speed and power challenges. Then, there has been a proliferation of standards. Take the Internet of Things (IoT) chips, for instance, where wireless standards like Bluetooth, Wi-Fi, ZigBee have become check-box items with the integration of IP subsystems.
A vantage point look at the evolution of SoC design over the course of a decade or so shows that the addition of more functions onto a single chip led to more complexity as well as time-to-market pressures. That made SoC segment an industry in a hurry. Chipmakers are now obliged to work around tight delivery schedules in the new IP-centric SoC model, and that makes the ever-growing library of IP content too hard to handle.
As a result, a new breed of semiconductor outfits have emerged that is benefitting from the growing complexity and time-to-market bottlenecks, and subsequently, the rising amount of IP in SoCs. One such company is ClioSoft Inc., the Fremont, California–based supplier of automated solutions for hardware configuration management of SoC designs.
Data management eases handling of disparate pieces of IP in SoC
ClioSoft, founded by Srinath Anantharaman in 1997, pioneered data and IP management for chip design on the lines similar to software configuration tools like Subversion. Anantharaman could see how precious chip engineering resources were spent on the manual handling of tasks like revision control, issue tracking and other gatekeeper functions.
ClioSoft’s first product—Save Our Software or SOS—managed the front-end RTL flows and eventually became a natural fit for data management in Cadence Virtuoso-based analog/mixed-signal designs. Over the years, the SoC design ecosystem continued to evolve and so did SOS tool as it added other popular analog/mixed-signal design flows such as Mentor Graphics Pyxis and Synopsys Custom Designer and Laker.
Then, in 2013, ClioSoft announced another milestone with the integration of its SOS tool into Agilent Technologies’ Advanced Design System (ADS) to provide version control and enterprise-wide management for RF and high-speed digital designs. That year, Agilent also spun off its test and measurement business as Keysight Technologies, which now owns and operates the prevalent RF design tool ADS.
ClioSoft’s SOS design collaboration platform is also winning attention from semiconductor IP suppliers, a crucial part of the chip design ecosystem. The steadily increasing use of IP in today’s bigger and more powerful SoCs means that IP vendors need to be more astute in customizing their products for different chipmakers and foundries, and do it in a time-efficient manner.
Not surprisingly, therefore, IP vendors are now increasingly using data and IP management tools like SOS to tag their products and hence map a specific IP from one chip client to another and from one foundry process to another. The design changes are happening on multiple fronts in an often geographically scattered SoC project, where design automation tools like ClioSoft SOS can play a critical role in efficiently managing the IP labyrinth.
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