WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 699
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 699
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
Synopsys
Posted on

Webinar: Optimizing QoR for FPGA Design

Webinar: Optimizing QoR for FPGA Design
by Bernard Murphy on 10-22-2017 at 12:00 pm
Categories: EDA, Events, FPGA, Synopsys

You might wonder why, in FPGA design, you would go beyond simply using the design tools provided by the FPGA vendor (e.g. Xilinx, Intel/Altera and Microsemi). After all, they know their hardware platform better than anyone else, and they’re pretty good at design software too. But there’s one thing none of these providers want to… Read More

Posted on

An Informal Update

An Informal Update
by Bernard Murphy on 10-05-2017 at 7:00 am
Categories: EDA, Synopsys

I mentioned back in June that Synopsys had launched a blog on formal verification, intended to demystify the field and provide help in understanding key concepts. It’s been a few months, time to check in on some of their more recent posts.


First up, it feels like they are finding their groove. Relaxed style, useful topics but now with… Read More

Posted on

Is there anything in VLSI layout other than pushing polygons? (2)

Is there anything in VLSI layout other than pushing polygons? (2)
by Dan Clein on 10-04-2017 at 12:00 pm
Categories: Cadence, Concept Engineering, General, Siemens EDA, Synopsys

One of the important changes that happen between 1984 and 1988 is the hardware platforms development. Calma evolved, mainframe S140 with 2 combined monitors per terminal in S280 with 2 individual monitors per terminal. This meant that from noisy and darker rooms we move to more quiet and lighted rooms. We doubled the speed and the… Read More

Posted on

How to Avoid Jeopardizing SoC Security when Implementing eSIM?

How to Avoid Jeopardizing SoC Security when Implementing eSIM?
by Eric Esteve on 09-26-2017 at 12:00 pm
Categories: EDA, IoT, Mobile, Security, Synopsys

Smart card business is now more than 25 years old, we can assess that the semiconductor industry is able to protect the chips used for smart card or SIM application with a very good level (unfortunately, it’s very difficult to get access to the fraud percentage linked with smart cards, as bankers really don’t like to communicate on… Read More

Posted on

Semiconductor and EDA 2017 Update!

Semiconductor and EDA 2017 Update!
by Daniel Nenni on 09-25-2017 at 7:00 am
Categories: Cadence, EDA, Synopsys

It really is an exciting time in semiconductors. The benchmarks on the new Apple A11 SoC and the Nvidia GPU are simply amazing. Even though Moore’s Law is slowing, the resulting chips are improving well above and beyond expectations, absolutely.

As I have mentioned before, non-traditional chip companies such as Apple, Amazon,… Read More

Posted on

Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am
Categories: EDA, Synopsys

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More

Posted on

Breakfast with Aart de Geus and the Foundries!

Breakfast with Aart de Geus and the Foundries!
by Daniel Nenni on 09-06-2017 at 7:00 am
Categories: Arm, EDA, Foundries, GlobalFoundries, Samsung Foundry, Synopsys, TSMC

Being the number one EDA and the number one IP company does have its advantages and the resulting foundry relationships are a clear example. One of the DAC traditions that I truly enjoy is the Synopsys foundry breakfasts. Not only does Synopsys welcome scribes, they reserve a table up front for us and Synopsys CEO Aart de Geus has been… Read More

Posted on

Bluetooth 5 IP is Ready for SoC Integration

Bluetooth 5 IP is Ready for SoC Integration
by Eric Esteve on 08-28-2017 at 7:00 am
Categories: IP, Synopsys

Bluetooth®, WiFi, LTE, and 5G technologies enable wireless connectivity for a range of applications. While each offer unique features and advantages, designers need now to decide which protocol to integrate in a single chip after having test the market by using wireless off-chip solutions. Bluetooth 5 builds upon the success… Read More

Posted on

Samsung, Synopsys and Qualcomm at DAC

Samsung, Synopsys and Qualcomm at DAC
by Daniel Payne on 08-24-2017 at 12:00 pm
Categories: EDA, FinFET, Samsung Foundry, Synopsys
20 Comments

I’m a user of many Samsung products as my family has Samsung Galaxy smart phones and my MacBook Pro uses Samsung SSD for storage, so at DAC I attended a breakfast panel with presenters from Samsung, Synopsys and Qualcomm. This was the second day of DAC and they served us breakfast, and with the big names on the panel the room was… Read More

Posted on

A Functional Safety Primer for FPGA – the White Paper

A Functional Safety Primer for FPGA – the White Paper
by Bernard Murphy on 08-23-2017 at 7:00 am
Categories: EDA, FPGA, Synopsys

Following up on their webinar on functional safety in FPGA-based designs, Synopsys have now published a white paper expanding on some of those topics. For those who didn’t get a chance to see the webinar this blog follows the white paper flow and is similar but not identical to my webinar blog, particularly around differences between… Read More