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Synopsys Webinar White 800x100 px Max Quality (1)
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The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)
by Lauro Rizzatti on 07-15-2024 at 10:00 am

Immensity of SW development Fig 1

Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.

Introduction

As the saying goes, it’s… Read More


LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis

LIVE WEBINAR Maximizing SoC Energy Efficiency: The Role of Realistic Workloads and Massively Parallel Power Analysis
by Daniel Nenni on 07-03-2024 at 2:00 pm

The Role of Realistic Workloads and Massively Parallel Power Analysis

As the complexity of modern System-on-Chip (SoC) designs continues to rise, achieving energy efficiency measured as performance per watt has become a crucial design goal. With the increasing demand for powerful, multifunctional chips, balancing performance with power consumption has become essential. Realistic workloads… Read More


Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure

Synopsys’ Strategic Advancement with PCIe 7.0: Early Access and Complete Solution for AI and Data Center Infrastructure
by Kalar Rajendiran on 06-25-2024 at 6:00 am

(From NewsRelease)Synopsys PCIe 7.0 IP Solution Infographic

In the rapidly evolving world of high-performance computing (HPC) and artificial intelligence (AI), technological advancements must keep pace with increasing demands for speed, efficiency, and security. Synopsys recently announced the industry’s first complete PCIe 7.0 IP solution. This groundbreaking initiative addresses… Read More


Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions

Synopsys-AMD Webinar: Advancing 3DIC Design Through Next-Generation Solutions
by Kalar Rajendiran on 06-13-2024 at 10:00 am

The Synopsys Multi Die Solution

Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended… Read More


Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification

Reduce Risk, Ensure Compliance: Hardware-Assisted Verification for Design Certification
by Lauro Rizzatti on 06-12-2024 at 10:00 am

Reduce risk ensure compliance Figure 1
Prologue

Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.Read More


What to Do with All that Data – AI-driven Analysis Can Help

What to Do with All that Data – AI-driven Analysis Can Help
by Rob vanBlommestein on 06-05-2024 at 10:00 am

1 design da

Today’s advanced node chip designs are faced with many new complexities from design and verification down to manufacturing. The solutions used at every stage of chip development generate petabytes of data. Managing, analyzing, understanding, and acting upon that data is overwhelming and paralyzing. Manual interpretation… Read More


Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems

Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems
by Mike Gianfagna on 06-03-2024 at 6:00 am

Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems

Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up of the ARC-V family on SemiWiki here. This is important and impactful news; I encourage you to read these articles if you haven’t… Read More


Synopsys Accelerates Innovation on TSMC Advanced Processes

Synopsys Accelerates Innovation on TSMC Advanced Processes
by Mike Gianfagna on 05-15-2024 at 10:00 am

Synopsys Accelerates Innovation on TSMC Advanced Processes

We all know that making advanced semiconductors is a team sport. TSMC can innovate the best processes, but without the right design flows, communication schemes and verified IP it becomes difficult to access those processes. Synopsys recently announced some details on this topic. It covers a lot of ground. The graphic at the top… Read More


SoC Power Islands Verification with Hardware-assisted Verification

SoC Power Islands Verification with Hardware-assisted Verification
by Lauro Rizzatti on 05-14-2024 at 10:00 am

SoC Power Islands Figure 1

The ever-growing demand for longer battery life in mobile devices and energy savings in general have pushed power optimization to the top of designers’ concerns. While various techniques like multi-VT transistors and clock gating offer power savings at gate-level design, the real impact occurs at system level, where hardware… Read More


ARC-V portfolio plus mature software IP targets three tiers

ARC-V portfolio plus mature software IP targets three tiers
by Don Dingee on 05-13-2024 at 10:00 am

ARC-V portfolio from Synopsys

Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs… Read More