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2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification

2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification
by Daniel Nenni on 03-25-2024 at 10:00 am

Dvcon 2024

2024 DVCon was very busy this year. Bernard Murphy and I were in attendance for SemiWiki, he has already written about it.  Multi die and chiplets was again a popular topic. Lauro Rizzatti, a consultant specializing in hardware-assisted verification, moderated an engaging panel, sponsored by Synopsys, focusing on the intricacies… Read More


Synopsys Enhances PPA with Backside Routing

Synopsys Enhances PPA with Backside Routing
by Mike Gianfagna on 03-19-2024 at 6:00 am

Comparison of frontside and backside PDNs (Source IMEC)

Complexity and density conspire to make power delivery very difficult for advanced SoCs. Signal integrity, power integrity, reliability and heat can seem to present unsolvable problems when it comes to efficient power management. There is just not enough room to get it all done with the routing layers available on the top side… Read More


Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips

Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips
by Kalar Rajendiran on 03-07-2024 at 10:00 am

Synopsys 1.6T Ethernet IP Solution Image 2

The demand for high-bandwidth, low-latency networking solutions has never been greater. As artificial intelligence (AI) workloads continue to grow exponentially, and hyperscale data centers become the backbone of our digital infrastructure, the need for faster and more efficient communication technologies becomes imperative.… Read More


2024 Signal & Power Integrity SIG Event Summary

2024 Signal & Power Integrity SIG Event Summary
by Daniel Nenni on 02-27-2024 at 10:00 am

SIG Event Synopsys

It was a dark and stormy night here in Silicon Valley but we still had a full room of semiconductor professionals. I emceed the event. In addition to demos, customer and partner presentations, we did a Q&A which was really great. One thing I have to say is that Intel really showed up for both DesignCon and the Chiplet Summit. Quite… Read More


Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
by Mike Gianfagna on 02-22-2024 at 10:00 am

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

The relentless demand for lower power SoCs is evident across many markets.  Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost… Read More


Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links
by Kalar Rajendiran on 02-22-2024 at 6:00 am

Simulation and Silicon ADC outpit scatter plot

In the relentless pursuit of ever-increasing data speeds, the 1.6 Terabits per second (Tbps) era looms on the horizon, promising unprecedented levels of connectivity and bandwidth within data centers. As data-intensive applications proliferate and the demand for real-time processing escalates, the need for robust and efficient… Read More


Why Did Synopsys Really Acquire Ansys?

Why Did Synopsys Really Acquire Ansys?
by Daniel Nenni on 01-25-2024 at 10:00 am

Synopsys Ansys Logos

Mergers and acquisitions have been a big part of EDA since the beginning. We keep an EDA/IP Mergers and Acquisitions Wiki, it is 13 years old now and has more than one million views. Personally, I have been involved with dozens of acquisitions over my 40 year career, some good, some bad, all are interesting and are an important part … Read More


Synopsys Geared for Next Era’s Opportunity and Growth

Synopsys Geared for Next Era’s Opportunity and Growth
by Kalar Rajendiran on 01-11-2024 at 6:00 am

SassineGhazi

As semiconductor industry folks know, Synopsys is a behemoth of a company. At $5.84B in FY2023 revenue (FY Nov-Oct), approximately 20,000 employees and a market cap of about $74B, it leads the silicon-to-systems design solutions space within the industry. From humble beginnings in 1986 as a disruptive startup, the company has… Read More


RISC-V and Chiplets: A Panel Discussion

RISC-V and Chiplets: A Panel Discussion
by Paul McLellan on 12-13-2023 at 10:00 am

rvnames

At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:

  • Laurent Moll, COO of Arteris
  • Aniket Saha, VP of Product Management of Tenstorrent
  • Dale Greenley, VP of Engineering of Ventana
Read More

Automated Constraints Promotion Methodology for IP to Complex SoC Designs

Automated Constraints Promotion Methodology for IP to Complex SoC Designs
by Kalar Rajendiran on 12-12-2023 at 6:00 am

Synopsys Timing Constraints Manager

In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More