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Semiconductor Fabrication Module Optimization

Semiconductor Fabrication Module Optimization
by Pawan Fangaria on 11-11-2013 at 9:00 am

The growing process integration complexity at each technology node has increased development time and cost, and this trend looks to continue. There is a looming risk of delivering unrepeatable critical unit processes (or process modules) that would require revisiting development and manufacturing requalification or in severe cases a design re-spin. Below the 22nm process node, tremendous effort is necessary to meet process integration specifications with a yielding process that is robust in the face of unavoidable manufacturing variation.

In one of my earlier articles here, I talked about a quick and automated way to optimize the complex BEOL (Back-End-Of-Line) metallization process through the use of Virtual Fabrication provided by a state-of-the-art tool, SEMulator3D from Coventor. A BEOL metallization whitepaperillustrates the SEMulator3D platform capability to assist with process development and optimization. SEMulator3D is an extremely powerful Virtual Fabrication tool to perform all types of tasks related to complete semiconductor chip manufacturing process, including FEOL (Front-End-Of-Line), MOL (Middle-Of-Line) and BEOL processes, quickly at your desk.

As Virtual Fabrication becomes increasingly important to help development keep pace with Moore’s Law, the semiconductor design and fabrication community are eager to understand more about how to leverage this technology. In the most straightforward sense, this means replacing costly and lengthy iterations of build-and-test learning with rapid virtual experimentation on a laptop. The ability to comprehensively map out an entire module space across all the critical structures on the device (in a matter of hours or days) is a significant innovation to help be the first to market with a new technology. Last month, Ryan J Patz from Coventor, author of BEOL metallization and patterning whitepapers, gave a very informative and detailed presentation on how Virtual Fabrication is done for BEOL module optimization below the 22nm technology node. The presentation was done live at AVS 60[SUP]th[/SUP] International Symposium & Exhibition. I was delighted to go through the presentation slides at the Coventor website here.

The talk provides a procedure for setting up a Virtual Fabrication process flow with automation for process module optimization. Mr. Patz presented example cases of how to use the SEMulator3D platform for identifying unexpected yield detractors, tuning cross-wafer uniformity, optimizing a process module for maximum yield and closed with a proposal to use Virtual Fabrication for feed-forward control to drive down run-to-run variation. Below, I am reproducing some of the key aspects of fabrication discussed in the presentation.


[Virtual Fabrication Automation Setup]

The above picture shows the automation capability to run a large number of experiments varying multiple parameters using a single spreadsheet-based input. Virtual Metrology collects all desired measurements from each model. It was noted that metrology not only includes the standard in-fab measurements (e.g. CD, film thickness) but also measurements that require destructive analysis on silicon, such as cross-section or interface area.


[Unit Process Tuning – Via Chamfer]

The above picture shows the results of a via chamfer study. The findings matched existing unit process trends, and Mr. Patz went on to discuss additional testing that could be done using Virtual Fabrication that is not easily done on silicon. For example, chamfer sensitivity to changes in CD or the Low-k porosity could be explored with simple changes to the inputs. This data cannot be generated on-wafer until the next technology generation. Results of these simulations give a better understanding of the process window and indication of future challenges.


[Process Interaction – TiN hard Mask Impact on Metallization]

The image above shows the trend of liner thickness for varying M2 TiN etch ratios. The large number of experiments gave insight into an unexpected process integration trend. The Cu cross-section area decreased with increased TiN etch rate, a change that was expected to improve Cu fill. Inspection of the 3D model revealed the effect was driven by a “shoulder” in the dielectric cap layer, resulting in a metallization profile degrade. This type of characterization helps to predict, and more quickly solve, yield issues that arise during a manufacturing ramp.

Digging further into process integration, the picture below shows how V1-M1 contact area varies with lithography. This model showed that a variation in the range of -3nm to +3nm in M1 lithography bias resulted in a 3x variation in contact area. The remainder of the presentation focused on understanding the drivers of V1-M1 contact area in order to minimize variation.


[V1-M1 contact area]


[Cross-Wafer Uniformity – V1-M1 Contact Area Baseline]

The general point was made that Virtual Fabrication is necessary to predict how all upstream process variation will impact a downstream process, such as V1-M1 contact area. This example showed upstream unit process variation resulted in a 5.9% 1s variation in the V1-M1 contact area. The key unit processes to control the contact area were identified, and an 1125-run experiment helped determine the steps in those unit processes most important for V1-M1 contact area.


[Cross-Wafer Tuning – Module Level Optimization]

Mr. Patz proposed retargeting the key unit process steps away from minimized non-uniformity to reduce the contact area variation. It was surprising to see that moving one of the steps in the V1-M2 etch from 0.0% to 20.7% 1s non-uniformity actually cut the V1-M1 contact area variation in half. This result was helpful to explain why understanding interactions within an entire module could be a key enabler for feed-forward process control.

Virtual Fabrication can help semiconductor design and process engineers characterize process variation sensitivity at the design stage, tune cross-wafer uniformity and optimize processes at a module level in much less time. This detailed characterization may even help bring in the era of automated process control (APC) and feed-forward process control to reduce device variation and improve yield. Have a look at the detailed presentation here. Also of interest would be another whitepaper on BEOL patterning. Happy learning!!

More Articles by Pawan Fangaria…..

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